On Tue, Nov 28, 2017 at 02:45:05PM +0000, Valtteri Rantala wrote: > Testing the texture read performance shows that the same tuning for > the SQ credits is needed on GLK as on BXT/APL. This has been also > confirmed by Altug from the HW team. > > V4: Rebase + fix > Signed-off-by: Valtteri Rantala <valtteri.rantala@xxxxxxxxx> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_engine_cs.c | 16 +++++++++------- > 1 file changed, 9 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index fede62d..0b04ca7 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); > > + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ > + if (IS_GEN9_LP(dev_priv)) { > + u32 val = I915_READ(GEN8_L3SQCREG1); > + > + val &= ~L3_PRIO_CREDITS_MASK; > + val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2); > + I915_WRITE(GEN8_L3SQCREG1, val); > + } > + > /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > GEN8_LQSC_FLUSH_COHERENT_LINES)); > @@ -1184,7 +1193,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) > static int bxt_init_workarounds(struct intel_engine_cs *engine) > { > struct drm_i915_private *dev_priv = engine->i915; > - u32 val; > int ret; > > ret = gen9_init_workarounds(engine); > @@ -1199,12 +1207,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) > I915_WRITE(FF_SLICE_CS_CHICKEN2, > _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE)); > > - /* WaProgramL3SqcReg1DefaultForPerf:bxt */ > - val = I915_READ(GEN8_L3SQCREG1); > - val &= ~L3_PRIO_CREDITS_MASK; > - val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2); > - I915_WRITE(GEN8_L3SQCREG1, val); > - > /* WaToEnableHwFixForPushConstHWBug:bxt */ > WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, > GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx