Quoting Chris Wilson (2017-11-22 15:32:33)
> A new context assumes that all of its registers are in the default state
> when it is created. What may happen is that a register written by one
> context may leak into the second, causing mass confusion.
>
> v2: Extend back to Sandybridge (etc)
> v3: Check context preserves registers across suspend/hibernate and resets.
> v4: Complete the remapping onto the new class:instance
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> ---
> tests/Makefile.sources | 1 +
> tests/gem_ctx_isolation.c | 672 ++++++++++++++++++++++++++++++++++++++++++++++
> tests/gem_exec_fence.c | 2 +-
> 3 files changed, 674 insertions(+), 1 deletion(-)
> create mode 100644 tests/gem_ctx_isolation.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index b4d4831e..57ecce6d 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -58,6 +58,7 @@ TESTS_progs = \
> gem_ctx_basic \
> gem_ctx_create \
> gem_ctx_exec \
> + gem_ctx_isolation \
> gem_ctx_param \
> gem_ctx_switch \
> gem_ctx_thrash \
> diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c
> new file mode 100644
> index 00000000..3478921c
> --- /dev/null
> +++ b/tests/gem_ctx_isolation.c
> @@ -0,0 +1,672 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "igt.h"
> +#include "igt_dummyload.h"
> +
> +#define MAX_REG 0x40000
> +#define NUM_REGS (MAX_REG / sizeof(uint32_t))
> +
> +#define PAGE_ALIGN(x) ALIGN(x, 4096)
> +
> +#define DIRTY1 0x1
> +#define DIRTY2 0x2
> +#define RESET 0x4
> +
> +enum {
> + RCS0 = 1 << (I915_ENGINE_CLASS_RENDER + 8),
> + BCS0 = 1 << (I915_ENGINE_CLASS_RENDER + 8),
> + VCS0 = 1 << (I915_ENGINE_CLASS_RENDER + 8),
> + VCS1 = 1 << (I915_ENGINE_CLASS_RENDER + 8) | 1,
> + VECS0 = 1 << (I915_ENGINE_CLASS_RENDER + 8),
> +};
> +
> +#define ALL ~0u
> +#define GEN_RANGE(x, y) ((ALL >> (32 - (y - x + 1))) << x)
> +#define GEN6 (ALL << 6)
> +#define GEN7 (ALL << 7)
> +#define GEN8 (ALL << 8)
> +#define GEN9 (ALL << 9)
> +
> +#define NOCTX 0
> +
> +#define LAST_KNOWN_GEN 10
> +
> +static const struct named_register {
> + const char *name;
> + unsigned int gen_mask;
> + unsigned int engine_mask;
> + uint32_t offset;
> + uint32_t count;
> +} safe_registers[] = {
> + { "NOPID", NOCTX, RCS0, 0x2094 },
> + { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
> + { "INSTPM", GEN9, RCS0, 0x20c0 },
> + { "IA_VERTICES_COUNT", GEN6, RCS0, 0x2310, 2 },
> + { "IA_PRIMITIVES_COUNT", GEN6, RCS0, 0x2318, 2 },
> + { "VS_INVOCATION_COUNT", GEN6, RCS0, 0x2320, 2 },
> + { "HS_INVOCATION_COUNT", GEN6, RCS0, 0x2300, 2 },
> + { "DS_INVOCATION_COUNT", GEN6, RCS0, 0x2308, 2 },
> + { "GS_INVOCATION_COUNT", GEN6, RCS0, 0x2328, 2 },
> + { "GS_PRIMITIVES_COUNT", GEN6, RCS0, 0x2330, 2 },
> + { "CL_INVOCATION_COUNT", GEN6, RCS0, 0x2338, 2 },
> + { "CL_PRIMITIVES_COUNT", GEN6, RCS0, 0x2340, 2 },
> + { "PS_INVOCATION_COUNT_0", GEN6, RCS0, 0x22c8, 2 },
> + { "PS_DEPTH_COUNT_0", GEN6, RCS0, 0x22d8, 2 },
> + { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
> + { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
> + { "GPUGPU_DISPATCHDIMZ", GEN8, RCS0, 0x2508 },
> + { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
> + { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
> + { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
> + { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
> + { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
> + { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
> + { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
> + { "3DPRIM_INSTANCE_COUNT", GEN6, RCS0, 0x2438 },
> + { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
> + { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
> + { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
> + { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
> + { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> + { "BB_OFFSET", GEN8, RCS0, 0x2158 },
> + { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
> + { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
> + { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> + { "OACTXID", GEN8, RCS0, 0x2364 },
> + { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
> + { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
> + { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
> + { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
> + { "GT_MODE", GEN8, RCS0, 0x7008 },
> + { "L3_Config", GEN7, RCS0, 0x7034 },
> + { "TD_CTL", GEN8, RCS0, 0xe400 },
> + { "TD_CTL2", GEN8, RCS0, 0xe404 },
> + { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
> + { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
> + { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
> + { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
> + { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
> + { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
> + { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
> + { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
> + { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
> + { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
> + { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
> + { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
> + { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
> + { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> + { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
> +
> + /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
> + { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
> + { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
> + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
> + { "L3SQREG1", GEN8, RCS0, 0xb010 },
> +
> + { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
> + { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
> +
> + { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
> + { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
> +
> + { "VCS1_GPR", GEN9, VCS1, 0x1c600, 32 },
> + { "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
> +
> + { "VECS_GPR", GEN9, VECS0, 0x1a600, 32 },
> +
> + {}
> +}, ignore_registers[] = {
> + { "RCS timestamp", GEN6, ~0u, 0x2358 },
> + { "VCS0 timestamp", GEN7, ~0u, 0x12358 },
> + { "VCS1 timestamp", GEN7, ~0u, 0x1c358 },
> + { "BCS timestamp", GEN7, ~0u, 0x22358 },
> + { "VECS timestamp", GEN8, ~0u, 0x1a358 },
> + {}
> +};
> +
> +static const char *register_name(uint32_t offset, char *buf, size_t len)
> +{
> + for (const struct named_register *r = safe_registers; r->name; r++) {
> + unsigned int width = r->count ? 4*r->count : 4;
> + if (offset >= r->offset && offset < r->offset + width) {
> + if (r->count <= 1)
> + return r->name;
> +
> + snprintf(buf, len, "%s[%d]",
> + r->name, (offset - r->offset)/4);
> + return buf;
> + }
> + }
> +
> + return "unknown";
> +}
> +
> +static bool ignore_register(uint32_t offset)
> +{
> + for (const struct named_register *r = ignore_registers; r->name; r++) {
> + unsigned int width = r->count ? 4*r->count : 4;
> + if (offset >= r->offset && offset < r->offset + width)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static uint32_t read_regs(int fd,
> + uint32_t ctx,
> + const struct intel_execution_engine2 *e,
> + unsigned int flags)
> +{
> + const int gen = intel_gen(intel_get_drm_devid(fd));
> + const unsigned int gen_bit = 1 << gen;
> + unsigned int engine_bit = (e->class + 8) | e->instance;
Did someone forget the BIT? He did.
-Chris
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