Quoting Tvrtko Ursulin (2017-11-22 12:46:22) > From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > > We add a PMU counter to expose the number of requests currently submitted > to the GPU, plus the number of runnable requests waiting on GPU time. > > This is useful to analyze the overall load of the system. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_pmu.c | 30 +++++++++++++++++++++++++----- > include/uapi/drm/i915_drm.h | 6 ++++++ > 2 files changed, 31 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 112243720ff3..b2b4b32af35f 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -36,7 +36,8 @@ > #define ENGINE_SAMPLE_MASK \ > (BIT(I915_SAMPLE_BUSY) | \ > BIT(I915_SAMPLE_WAIT) | \ > - BIT(I915_SAMPLE_SEMA)) > + BIT(I915_SAMPLE_SEMA) | \ > + BIT(I915_SAMPLE_QUEUED)) > > #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS) > > @@ -223,6 +224,12 @@ static void engines_sample(struct drm_i915_private *dev_priv) > > update_sample(&engine->pmu.sample[I915_SAMPLE_SEMA], > PERIOD, !!(val & RING_WAIT_SEMAPHORE)); > + > + if (engine->pmu.enable & BIT(I915_SAMPLE_QUEUED)) > + update_sample(&engine->pmu.sample[I915_SAMPLE_QUEUED], > + 1 / I915_SAMPLE_QUEUED_SCALE, > + engine->queued + READ_ONCE(engine->queued) to indicate that this is outside of its lock. Useful to indicate that we haven't serialised it with last_seqno. (And no serialisation can be done against current_seqno ;) -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
