Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_pci.c | 3 +--
drivers/gpu/drm/i915/intel_pm.c | 28 ++++++++++++++++++++++++++++
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f1c6756440a9..e0458dff0371 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -216,8 +216,7 @@ static const struct intel_device_info intel_gm45_info __initconst = {
static const struct intel_device_info intel_ironlake_d_info __initconst = {
GEN5_FEATURES,
.platform = INTEL_IRONLAKE,
- /* ilk does support rc6, but we do not implement [power] contexts */
- .has_rc6 = 0,
+ .has_rc6 = true,
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1d46b7ed2cf..345127b55afd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6378,6 +6378,30 @@ static void gen9_disable_rps(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RP_CONTROL, 0);
}
+static void gen5_enable_rc6(struct drm_i915_private *dev_priv)
+{
+ u32 offset =
+ i915_ggtt_offset(dev_priv->kernel_context->engine[RCS].state);
+
+ I915_WRITE(PWRCTXA, offset | PWRCTX_EN);
+ I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+}
+
+static void gen5_disable_rc6(struct drm_i915_private *dev_priv)
+{
+ /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
+ I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
+ intel_wait_for_register(dev_priv,
+ RSTDBYCTL,
+ RSX_STATUS_MASK, RSX_STATUS_ON,
+ 50);
+ I915_WRITE(PWRCTXA, 0);
+ POSTING_READ(PWRCTXA);
+
+ I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+ POSTING_READ(RSTDBYCTL);
+}
+
static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
{
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7982,6 +8006,8 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
valleyview_disable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rc6(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 5)
+ gen5_disable_rc6(dev_priv);
dev_priv->gt_pm.rc6.enabled = false;
}
@@ -8048,6 +8074,8 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
gen8_enable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_enable_rc6(dev_priv);
+ else if (INTEL_GEN(dev_priv) >= 5)
+ gen5_enable_rc6(dev_priv);
dev_priv->gt_pm.rc6.enabled = true;
}
--
2.15.0
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