Quoting Rafael Antognolli (2017-11-13 16:20:39)
> On Sat, Nov 11, 2017 at 10:03:36AM +0000, Chris Wilson wrote:
> > gem_workarounds reports that the SLICE_UNIT_LEVEL_CLKGATE write isn't
> > sticking. Commit 0a60797a0efb ("drm/i915: Implement
> > ReadHitWriteOnlyDisable.") presumes that SLICE_UNIT_LEVEL_CLKGATE is a
> > masked register in the context image, but commit 90007bca6162
> > ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") lists it as
> > an ordering unmasked register. The masked write will be losing the
> > default settings if we trust the original commit. That gem_workarounds
> > reports the value is lost entirely is more worrying though -- but it
> > clearly suggests that it is not a masked register in the context image,
> > so unify both w/a to use the original rmw.
>
> Thanks for fixing this.
>
> Reviewed-by: Rafael Antognolli <rafael.antognolli@xxxxxxxxx>
So I am not 100% confident that the register write is sticking, but
applying the two w/a together does at least mean one isn't overwriting
the other!
We shall revisit this when we have the generic w/a checker. Thanks for
the review, pushed with bugzilla tag.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
