On Mon, Nov 13, 2017 at 03:40:43PM +0100, Maarten Lankhorst wrote:
> The firmware may have set up the pipe correctly, but the FIFO
> underrun and CRC interrupts are likely not enabled.
>
> This resulted in debugfs_test.read_all_entries failing on haswell,
> because of a timeout when reading the crc debugfs entry.
>
> Solve this by enabling FIFO underrun reporting after the initial
> fastset, which lets interrupts be generated as expected.
>
> Changes since v1:
> - Always enable CPU FIFO underrun reporting for >GEN2,
> and handle GEN2 correctly.
> Changes since v2:
> - Remove unneeded HAS_DDI, simplify GEN2 case.
> Changes since v3:
> - Use intel_crtc_pch_transcoder to determine pch transcoder for underruns. (Ville)
> - Remove crtc->config dereference in intel_crtc_pch_transcoder. (Ville)
>
> Testcase: debugfs_test.read_all_entries
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 03e274a11d95..e49ee9d3bd61 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1872,8 +1872,6 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - WARN_ON(!crtc->config->has_pch_encoder);
> -
> if (HAS_PCH_LPT(dev_priv))
> return PIPE_A;
> else
> @@ -12908,6 +12906,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
> static void intel_finish_crtc_commit(struct drm_crtc *crtc,
> struct drm_crtc_state *old_crtc_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_atomic_state *old_intel_state =
> to_intel_atomic_state(old_crtc_state->state);
> @@ -12915,6 +12914,20 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc,
> intel_atomic_get_new_crtc_state(old_intel_state, intel_crtc);
>
> intel_pipe_update_end(new_crtc_state);
> +
> + if (new_crtc_state->update_pipe &&
> + !needs_modeset(&new_crtc_state->base) &&
> + old_crtc_state->mode.private_flags & I915_MODE_FLAG_INHERITED) {
> + if (!IS_GEN2(dev_priv))
> + intel_set_cpu_fifo_underrun_reporting(dev_priv, intel_crtc->pipe, true);
> +
> + if (new_crtc_state->has_pch_encoder) {
> + enum pipe pch_transcoder =
> + intel_crtc_pch_transcoder(dev_priv, intel_crtc);
> +
> + intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
> + }
> + }
> }
>
> /**
> --
> 2.15.0
--
Ville Syrjälä
Intel OTC
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