On Wed, Nov 08, 2017 at 03:30:16PM -0800, Rodrigo Vivi wrote:
> PM Rsp is not sent when plane is turned off at around the
> time that a PM fill Req is received by display
Do we know what the impact of this is? The HSD just seems to say
"Detection method: Hang" which isn't partciluarly helpful.
To me this smells vaguely of WaRsPkgCStateDisplayPMReq:hsw which
will cause a system hang if we don't do it early enough. Do we have
similar concerns here? (and if so please look at commit f72b84c677d6
("drm/i915: Move init_clock_gating() back to where it was"))
Maybe we should start a new init_clock_gating/init_workarounds thing
just for the display, and add all new stuff there? And then we can
start moving the old display w/as etc. there as well.
>
> WA: disable arbiter clock gating, set bit [27] of 0x46530
>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6ef33422f762..fc8c5f8260f6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3819,6 +3819,7 @@ enum {
> * GEN9 clock gating regs
> */
> #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
> +#define DARBF_GATING_DIS (1 << 27)
> #define PWM2_GATING_DIS (1 << 14)
> #define PWM1_GATING_DIS (1 << 13)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e09377df590d..e642e8983035 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -127,6 +127,10 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> u32 val;
> gen9_init_clock_gating(dev_priv);
>
> + /* Display WA #1185 WaDisableDARBFClkGating:glk */
> + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> + DARBF_GATING_DIS);
> +
> /*
> * WaDisablePWMClockGating:glk
> * Backlight PWM may stop in the asserted state, causing backlight
> @@ -8528,6 +8532,10 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
> u32 val;
> cnp_init_clock_gating(dev_priv);
>
> + /* Display WA #1185 WaDisableDARBFClkGating:cnl */
> + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> + DARBF_GATING_DIS);
> +
> /* This is not an Wa. Enable for better image quality */
> I915_WRITE(_3D_CHICKEN3,
> _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> --
> 2.13.6
>
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--
Ville Syrjälä
Intel OTC
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