On Fri, Nov 03, 2017 at 06:30:27PM +0000, Rafael Antognolli wrote:
> The workaround for this is described as:
>
> "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
>
> Further documentation in the internal bug referenced by the bspec
> suggest that any of the above suggestions should suffice to fix the
> issue. We are going with disabling RCC clock gating.
>
> Unfortunately, what we are doing doesn't match the name of the
> workaround, but at least it matches its description.
>
> This change improves CNL stability by avoiding some of the hangs seen in
> the platform.
>
> v2: Only disable RCC clock gating.
>
> Signed-off-by: Rafael Antognolli <rafael.antognolli@xxxxxxxxx>
Merged to dinq. Thanks for the patch.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c775e96b4e4..bd36ec9bc93f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3837,6 +3837,7 @@ enum {
> */
> #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> +#define RCCUNIT_CLKGATE_DIS (1 << 7)
>
> /*
> * Display engine regs
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f31f2d6384c3..3af0dcb91e9c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>
> + /* ReadHitWriteOnlyDisable: cnl */
> + WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> +
> /* WaEnablePreemptionGranularityControlByUMD:cnl */
> I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> --
> 2.13.6
>
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