Quoting Matthew Auld (2017-11-07 16:24:47) > On 7 November 2017 at 11:56, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > > Since the partial tiling tests are poking into the GGTT to watch the > > fence registers in operation, it itself needs the device rpm wakeref in > > order for the GGTT to remain accessible. > > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > Reviewed-by: Matthew Auld <matthew.auld@xxxxxxxxx> Pushed, thanks for the review. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
