To their rightful place inside intel_workarounds.c
v2:
- Rebase on WA removed
- Rebased to carry the init_early nomenclature over (Chris)
v3: Static tables
Signed-off-by: Oscar Mateo <oscar.mateo@xxxxxxxxx>
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> (v1)
Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 48 --------------------------------
drivers/gpu/drm/i915/intel_workarounds.c | 28 +++++++++++++++++++
2 files changed, 28 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ff3ac6c..f712b02 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -57,50 +57,8 @@
#define INTEL_RC6p_ENABLE (1<<1)
#define INTEL_RC6pp_ENABLE (1<<2)
-static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- if (HAS_LLC(dev_priv)) {
- /*
- * WaCompressedResourceDisplayNewHashMode:skl,kbl
- * Display WA#0390: skl,kbl
- *
- * Must match Sampler, Pixel Back End, and Media. See
- * WaCompressedResourceSamplerPbeMediaNewHashMode.
- */
- I915_WRITE(CHICKEN_PAR1_1,
- I915_READ(CHICKEN_PAR1_1) |
- SKL_DE_COMPRESSED_HASH_MODE);
- }
-
- /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
- I915_WRITE(CHICKEN_PAR1_1,
- I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
-
- /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
- I915_WRITE(GEN8_CHICKEN_DCPR_1,
- I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-
- /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
- /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
- I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
- DISP_FBC_WM_DIS |
- DISP_FBC_MEMORY_WAKE);
-
- /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
- I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
- ILK_DPFC_DISABLE_DUMMY0);
-
- if (IS_SKYLAKE(dev_priv)) {
- /* WaDisableDopClockGating */
- I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
- & ~GEN7_DOP_CLOCK_GATE_ENABLE);
- }
-}
-
static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
{
- gen9_init_clock_gating(dev_priv);
-
/* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@@ -123,7 +81,6 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
{
u32 val;
- gen9_init_clock_gating(dev_priv);
/*
* WaDisablePWMClockGating:glk
@@ -8522,7 +8479,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
{
cnp_init_clock_gating(dev_priv);
- gen9_init_clock_gating(dev_priv);
/* WaFbcNukeOnHostModify:cfl */
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
@@ -8531,8 +8487,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
{
- gen9_init_clock_gating(dev_priv);
-
/* WaDisableSDEUnitClockGating:kbl */
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
@@ -8550,8 +8504,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
{
- gen9_init_clock_gating(dev_priv);
-
/* WAC6entrylatency:skl */
I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
FBC_LLC_FULLY_OPEN);
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index a0b34d9..d5cbda1 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -889,9 +889,37 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
};
static struct i915_wa_reg gen9_disp_was[] = {
+ /*
+ * Must match Sampler, Pixel Back End, and Media. See
+ * WaCompressedResourceSamplerPbeMediaNewHashMode.
+ */
+ { WA_DISP("WaCompressedResourceDisplayNewHashMode + Display WA#0390"),
+ ALL_REVS, REG(CHICKEN_PAR1_1),
+ SET_BIT(SKL_DE_COMPRESSED_HASH_MODE),
+ .pre_hook = has_llc },
+
+ /* See Bspec note for PSR2_CTL bit 31 */
+ { WA_DISP("Wa#828"),
+ ALL_REVS, REG(CHICKEN_PAR1_1),
+ SET_BIT(SKL_EDP_PSR_FIX_RDWRAP) },
+
+ { WA_DISP("WaEnableChickenDCPR"),
+ ALL_REVS, REG(GEN8_CHICKEN_DCPR_1),
+ SET_BIT(MASK_WAKEMEM) },
+
+ { WA_DISP("WaFbcTurnOffFbcWatermark + WaFbcWakeMemOn "),
+ ALL_REVS, REG(DISP_ARB_CTL),
+ SET_BIT(DISP_FBC_WM_DIS | DISP_FBC_MEMORY_WAKE) },
+
+ { WA_DISP("WaFbcHighMemBwCorruptionAvoidance"),
+ ALL_REVS, REG(ILK_DPFC_CHICKEN),
+ SET_BIT(ILK_DPFC_DISABLE_DUMMY0) },
};
static struct i915_wa_reg skl_disp_was[] = {
+ { WA_DISP("WaDisableDopClockGating"),
+ ALL_REVS, REG(GEN7_MISCCPCTL),
+ CLEAR_BIT(GEN7_DOP_CLOCK_GATE_ENABLE) },
};
static struct i915_wa_reg bxt_disp_was[] = {
--
1.9.1
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