To their rightful place inside intel_workarounds.c
v2: classify WaSarbUnitClockGatingDisable as GT WA (Ville)
v3: Static tables
Signed-off-by: Oscar Mateo <oscar.mateo@xxxxxxxxx>
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> (v1)
Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 32 +-------------------------------
drivers/gpu/drm/i915/intel_workarounds.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 33 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0d0e84b..ff3ac6c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8519,36 +8519,6 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
CNP_PWM_CGE_GATING_DISABLE);
}
-static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- u32 val;
- cnp_init_clock_gating(dev_priv);
-
- /* This is not an Wa. Enable for better image quality */
- I915_WRITE(_3D_CHICKEN3,
- _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
-
- /* WaEnableChickenDCPR:cnl */
- I915_WRITE(GEN8_CHICKEN_DCPR_1,
- I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
-
- /* WaFbcWakeMemOn:cnl */
- I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
- DISP_FBC_MEMORY_WAKE);
-
- /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
- if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
- I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
- I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
- SARBUNIT_CLKGATE_DIS);
-
- /* Display WA #1133: WaFbcSkipSegments:cnl */
- val = I915_READ(ILK_DPFC_CHICKEN);
- val &= ~GLK_SKIP_SEG_COUNT_MASK;
- val |= GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1);
- I915_WRITE(ILK_DPFC_CHICKEN, val);
-}
-
static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
{
cnp_init_clock_gating(dev_priv);
@@ -9040,7 +9010,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_CANNONLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cnl_init_clock_gating;
+ dev_priv->display.init_clock_gating = nop_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 72e8d90..a0b34d9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -779,6 +779,15 @@ static uint mmio_workarounds_apply(struct drm_i915_private *dev_priv,
{ WA_GT("WaEnablePreemptionGranularityControlByUMD"),
ALL_REVS, REG(GEN7_FF_SLICE_CS_CHICKEN1),
SET_BIT_MASKED(GEN9_FFSC_PERCTX_PREEMPT_CTRL) },
+
+ /* This is not an Wa. Enable for better image quality */
+ { WA_GT(""),
+ ALL_REVS, REG(_3D_CHICKEN3),
+ SET_BIT_MASKED(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE) },
+
+ { WA_GT("WaSarbUnitClockGatingDisable (pre-prod)"),
+ REVS(CNL_REVID_A0, CNL_REVID_B0), REG(SLICE_UNIT_LEVEL_CLKGATE),
+ SET_BIT(SARBUNIT_CLKGATE_DIS) },
};
static const struct i915_wa_reg_table bdw_gt_wa_tbl[] = {
@@ -894,10 +903,33 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
static struct i915_wa_reg glk_disp_was[] = {
};
+static bool has_pch_cnp(struct drm_i915_private *dev_priv,
+ struct i915_wa_reg *wa)
+{
+ return HAS_PCH_CNP(dev_priv);
+}
+
static struct i915_wa_reg cfl_disp_was[] = {
};
static struct i915_wa_reg cnl_disp_was[] = {
+ { WA_DISP("Wa #1181"),
+ ALL_REVS, REG(SOUTH_DSPCLK_GATE_D),
+ SET_BIT(CNP_PWM_CGE_GATING_DISABLE),
+ .pre_hook = has_pch_cnp },
+
+ { WA_DISP("WaEnableChickenDCPR"),
+ ALL_REVS, REG(GEN8_CHICKEN_DCPR_1),
+ SET_BIT(MASK_WAKEMEM) },
+
+ { WA_DISP("WaFbcWakeMemOn"),
+ ALL_REVS, REG(DISP_ARB_CTL),
+ SET_BIT(DISP_FBC_MEMORY_WAKE) },
+
+ { WA_DISP("Display WA #1133: WaFbcSkipSegments"),
+ ALL_REVS, REG(ILK_DPFC_CHICKEN),
+ SET_FIELD(GLK_SKIP_SEG_COUNT_MASK,
+ GLK_SKIP_SEG_EN | GLK_SKIP_SEG_COUNT(1)) },
};
static const struct i915_wa_reg_table bdw_disp_wa_tbl[] = {
--
1.9.1
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