> On 11/3/2017 3:05 PM, Michal Wajdeczko wrote:
> > We unconditionally program GUC_SHIM_CONTROL register with
> > diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
> > index 74a61fe..3f013f7 100644
> > --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> > +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> > @@ -100,15 +100,22 @@ int intel_guc_fw_select(struct intel_guc *guc)
> > static void guc_prepare_xfer(struct intel_guc *guc)
> > {
> > struct drm_i915_private *dev_priv = guc_to_i915(guc);
> > + u32 shim_control_value;
> >
> > - /* Enable MIA caching. GuC clock gating is disabled. */
> > - I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
> > + /* Expected bits for normal operation */
> > + shim_control_value = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
> > + GUC_ENABLE_READ_CACHE_LOGIC |
> > + GUC_ENABLE_MIA_CACHING |
> > + GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
> > + GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
> > + GUC_ENABLE_MIA_CLOCK_GATING;
> >
> > /* WaDisableMinuteIaClockGating:bxt */
> > - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> > - I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
> > - ~GUC_ENABLE_MIA_CLOCK_GATING));
> > - }
> > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > + shim_control_value &= ~GUC_ENABLE_MIA_CLOCK_GATING;
> > +
Do you want to before changing this process, rip out the preproduction
steps?
-Chris
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