Let's try to make sure that all WAs are applied correctly and survive
resumes, resets, etc... (with some help from a companion i-g-t patch).
v2:
- Rebased
- Print display WAs as well (Ville)
v3:
- Grab the forcewake once for everyone, so that all reads are from
the same powercontext (Chris)
Signed-off-by: Oscar Mateo <oscar.mateo@xxxxxxxxx>
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_debugfs.c | 59 ++++++++++++++++++++++++++++---------
1 file changed, 45 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2890c02..03ae750 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3355,6 +3355,22 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
return 0;
}
+static void check_wa_register(struct seq_file *m, struct i915_wa_reg *wa_reg)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ u32 read;
+ bool ok;
+
+ assert_forcewakes_active(dev_priv, FORCEWAKE_ALL);
+
+ read = I915_READ_FW(wa_reg->addr);
+ ok = (wa_reg->value & wa_reg->mask) == (read & wa_reg->mask);
+ seq_printf(m, "0x%X: 0x%08x, mask: 0x%08x, read: 0x%08x, status: %s\n",
+ i915_mmio_reg_offset(wa_reg->addr),
+ wa_reg->value, wa_reg->mask, read,
+ ok ? "OK" : "FAIL");
+}
+
static int i915_wa_registers(struct seq_file *m, void *unused)
{
int i;
@@ -3364,6 +3380,7 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
struct drm_device *dev = &dev_priv->drm;
struct i915_workarounds *workarounds = &dev_priv->workarounds;
enum intel_engine_id id;
+ u32 whitelist_wa_count = 0;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
@@ -3372,22 +3389,36 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
intel_runtime_pm_get(dev_priv);
seq_printf(m, "Context workarounds applied: %d\n", workarounds->ctx_wa_count);
- for_each_engine(engine, dev_priv, id)
- seq_printf(m, "HW whitelist count for %s: %d\n",
- engine->name, workarounds->whitelist_wa_count[id]);
for (i = 0; i < workarounds->ctx_wa_count; ++i) {
- i915_reg_t addr;
- u32 mask, value, read;
- bool ok;
-
- addr = workarounds->ctx_wa_reg[i].addr;
- mask = workarounds->ctx_wa_reg[i].mask;
- value = workarounds->ctx_wa_reg[i].value;
- read = I915_READ(addr);
- ok = (value & mask) == (read & mask);
- seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
- i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
+ struct i915_wa_reg *wa_reg = &workarounds->ctx_wa_reg[i];
+
+ seq_printf(m, "0x%X: 0x%08x, mask: 0x%08x\n",
+ i915_mmio_reg_offset(wa_reg->addr),
+ wa_reg->value, wa_reg->mask);
}
+ seq_putc(m, '\n');
+
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ seq_printf(m, "GT workarounds applied: %d\n", workarounds->gt_wa_count);
+ for (i = 0; i < workarounds->gt_wa_count; ++i)
+ check_wa_register(m, &workarounds->gt_wa_reg[i]);
+ seq_putc(m, '\n');
+
+ seq_printf(m, "Display workarounds applied: %d\n", workarounds->display_wa_count);
+ for (i = 0; i < workarounds->display_wa_count; ++i)
+ check_wa_register(m, &workarounds->display_wa_reg[i]);
+ seq_putc(m, '\n');
+
+ for_each_engine(engine, dev_priv, id)
+ whitelist_wa_count += workarounds->whitelist_wa_count[id];
+ seq_printf(m, "Whitelist workarounds applied: %d\n", whitelist_wa_count);
+ for_each_engine(engine, dev_priv, id)
+ for (i = 0; i < workarounds->whitelist_wa_count[id]; ++i)
+ check_wa_register(m, &workarounds->whitelist_wa_reg[id][i]);
+ seq_putc(m, '\n');
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
intel_runtime_pm_put(dev_priv);
mutex_unlock(&dev->struct_mutex);
--
1.9.1
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