On Fri, 27 Oct 2017, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > On Fri, Oct 27, 2017 at 01:25:01PM +0300, Jani Nikula wrote: >> On Mon, 14 Aug 2017, Harry Wentland <harry.wentland@xxxxxxx> wrote: >> > On 2017-08-11 02:10 PM, Dhinakaran Pandiyan wrote: >> >> DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state >> >> >> >> 101 = Set Main-Link for local Sink device and all downstream Sink >> >> devices to D3 (power-down mode), keep AUX block fully powered, ready to >> >> reply within a Response Timeout period of 300us. >> >> >> >> This state is useful in a MST dock + MST monitor configuration that >> >> doesn't wake up from D3 state. >> >> >> >> v2: Use spaces instead of tabs (Jani) >> >> >> >> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> >> > >> > Reviewed-by: Harry Wentland <harry.wentland@xxxxxxx> >> >> Pushed this one to drm-misc-next, thanks for the patch and review, and >> sorry for the delay. > > Sorry to start reviewing after this got pushed, but... > >> >> BR, >> Jani. >> >> > >> > Harry >> > >> >> --- >> >> include/drm/drm_dp_helper.h | 1 + >> >> 1 file changed, 1 insertion(+) >> >> >> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> >> index b17476a..47a6cdb 100644 >> >> --- a/include/drm/drm_dp_helper.h >> >> +++ b/include/drm/drm_dp_helper.h >> >> @@ -618,6 +618,7 @@ >> >> # define DP_SET_POWER_D0 0x1 >> >> # define DP_SET_POWER_D3 0x2 >> >> # define DP_SET_POWER_MASK 0x3 > > This mask doesn't cover the "aux" bit. I guess it's a purely theoretical > concern at this point since the device should start out in D0 when > first plugged in. > > Also IIRC this stuff was added in DPCD 1.2. We might want a comment to > reflect that fact. Okay, the damage is done, someone(tm) please send fixup patches on top to make it right. BR, Jani. > >> >> +# define DP_SET_POWER_D3_AUX_ON 0x5 >> >> >> >> #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ >> >> # define DP_EDP_11 0x00 >> >> >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> -- >> Jani Nikula, Intel Open Source Technology Center >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
