Re: [PATCH] drm/i915/vbt: Fix HDMI level shifter and max data rate bitfield sizes

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On Fri, 27 Oct 2017, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The HDMI level shifter value should be 5 bits and the max data rate 3 bits.
>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> Reported-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>

Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>

> ---
>  drivers/gpu/drm/i915/intel_vbt_defs.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index f225c288a121..3c3c421e2e43 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -342,8 +342,8 @@ struct child_device_config {
>  			u8 i2c_speed;
>  			u8 dp_onboard_redriver;			/* 158 */
>  			u8 dp_ondock_redriver;			/* 158 */
> -			u8 hdmi_level_shifter_value:4;		/* 169 */
> -			u8 hdmi_max_data_rate:4;		/* 204 */
> +			u8 hdmi_level_shifter_value:5;		/* 169 */
> +			u8 hdmi_max_data_rate:3;		/* 204 */
>  			u16 dtd_buf_ptr;			/* 161 */
>  			u8 edidless_efp:1;			/* 161 */
>  			u8 compression_enable:1;		/* 198 */

-- 
Jani Nikula, Intel Open Source Technology Center
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