On Thu, Oct 26, 2017 at 02:11:22PM +0100, Chris Wilson wrote: > Quoting Ville Syrjälä (2017-10-26 13:59:05) > > On Thu, Oct 26, 2017 at 01:12:12PM +0100, Chris Wilson wrote: > > > Some machines, *cough* snb *cough*, fail catastrophically if asked to > > > reset the GPU under certain conditions. > > > > Did we try skipping the gen6_rps_disable() already? > > I had thought we had taken that out a while ago... > > commit f2a91d1a6f5960c08f1ca60bd076f4dc020c50c6 > Author: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Date: Wed Sep 21 14:51:06 2016 +0100 > > drm/i915: Restore current RPS state after reset > > removes the frobbing inside i915_reset() itself, but still talks about > RPS needing to be restored... Ok, that's the post-reset stuff to make > sure that the hw/sw tracking align. Hmm. Right. It looks like we do the disable+re-enable back to back after the reset. I guess at that point it should be safe, assuming the reset actually worked. > > We are not touching rc6/rps prior to hitting GDRST. Maybe we should? Based on what I remember that would be more dangerous if the engined is stuck in a bad way. So I guess these reset problems are something else then. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
