On Tue, Oct 24, 2017 at 09:52:15AM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> chv_set_cdclk() sanity checks that the cdclk frequency is one of the
> legal values. Do the same in the VLV function.
thanks for spliting in separated patch.
>
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 4ca4a34b7bfa..fedfe3c720b6 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -520,6 +520,18 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> int cdclk = cdclk_state->cdclk;
> u32 val, cmd = cdclk_state->voltage_level;
>
> + switch (cdclk) {
> + case 400000:
> + case 333333:
> + case 320000:
> + case 266667:
> + case 200000:
values match vlv_calc_cdclk
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> + break;
> + default:
> + MISSING_CASE(cdclk);
> + return;
> + }
> +
> /* There are cases where we can end up here with power domains
> * off and a CDCLK frequency other than the minimum, like when
> * issuing a modeset without actually changing any display after
> --
> 2.13.6
>
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