On Fri, Oct 20, 2017 at 05:05:40PM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> On CNL we may need to bump up the system agent voltage not only due
> to CDCLK but also when driving DDI port with a sufficiently high clock.
> To that end start tracking the minimum acceptable voltage for each crtc.
> We do the tracking via crtcs because we don't have any kind of encoder
> state. Also there's no downside to doing it this way, and it matches how
> we track cdclk requirements on account of pixel rate.
>
> v2: Allow disabled crtcs to use the min voltage
> Add IS_CNL check to intel_ddi_compute_min_voltage() since
> we're using CNL specific values there
> s/intel_compute_min_voltage/cnl_compute_min_voltage/ since
> the function makes hw specific assumptions about the voltage
> values
> v3: Drop the test hack leftovers from skl_modeset_calc_cdclk()
>
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_cdclk.c | 46 +++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++
> drivers/gpu/drm/i915/intel_display.c | 9 +++++++
> drivers/gpu/drm/i915/intel_dp_mst.c | 5 ++++
> drivers/gpu/drm/i915/intel_drv.h | 6 +++++
> 6 files changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d3ac58dc275f..185711a852b0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2415,6 +2415,8 @@ struct drm_i915_private {
> unsigned int active_crtcs;
> /* minimum acceptable cdclk for each pipe */
> int min_cdclk[I915_MAX_PIPES];
> + /* minimum acceptable voltage for each pipe */
> + u8 min_voltage[I915_MAX_PIPES];
>
> int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 2a0cc9aafa5a..0f5f2ce4bd3e 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1661,6 +1661,12 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
> mutex_unlock(&dev_priv->pcu_lock);
>
> intel_update_cdclk(dev_priv);
> +
> + /*
> + * Can't read out the voltage :( So let's
> + * just assume everything is as expected.
> + */
> + dev_priv->cdclk.hw.voltage = cdclk_state->voltage;
> }
>
> static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> @@ -1930,6 +1936,42 @@ static int intel_compute_min_cdclk(struct drm_atomic_state *state)
> return min_cdclk;
> }
>
> +/*
> + * Note that this functions assumes that 0 is
> + * the lowest voltage value, and higher values
> + * correspond to increasingly higher voltages.
> + *
> + * Should that relationship no longer hold on
> + * future platforms this code will need to be
> + * adjusted.
> + */
> +static u8 cnl_compute_min_voltage(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
> + u8 min_voltage;
> + int i;
> + enum pipe pipe;
> +
> + memcpy(state->min_voltage, dev_priv->min_voltage,
> + sizeof(state->min_voltage));
> +
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> + if (crtc_state->base.enable)
> + state->min_voltage[i] = crtc_state->min_voltage;
> + else
> + state->min_voltage[i] = 0;
> + }
> +
> + min_voltage = 0;
> + for_each_pipe(dev_priv, pipe)
> + min_voltage = max(state->min_voltage[pipe],
> + min_voltage);
> +
> + return min_voltage;
> +}
> +
> static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->dev);
> @@ -2086,7 +2128,9 @@ static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> intel_state->cdclk.logical.vco = vco;
> intel_state->cdclk.logical.cdclk = cdclk;
> - intel_state->cdclk.logical.voltage = cnl_calc_voltage(cdclk);
> + intel_state->cdclk.logical.voltage =
> + max(cnl_calc_voltage(cdclk),
> + cnl_compute_min_voltage(intel_state));
>
> if (!intel_state->active_crtcs) {
> cdclk = cnl_calc_cdclk(0);
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index adf51b328844..f707134b4f65 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2525,6 +2525,13 @@ bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
> return false;
> }
>
> +void intel_ddi_compute_min_voltage(struct drm_i915_private *dev_priv,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
> + crtc_state->min_voltage = 2;
> +}
Now we have this properly handled, should we remove on the same patch
all 4 "FIXME: (DVFS)" on dpll code? Maybe removing the entire comment
blocks with a smaller explanation that we handle that dvfs in a different
and atomic way.
one way or another, feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> +
> void intel_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> @@ -2624,6 +2631,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
> if (IS_GEN9_LP(dev_priv))
> pipe_config->lane_lat_optim_mask =
> bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
> +
> + intel_ddi_compute_min_voltage(dev_priv, pipe_config);
> }
>
> static bool intel_ddi_compute_config(struct intel_encoder *encoder,
> @@ -2650,6 +2659,8 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
> bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
> pipe_config->lane_count);
>
> + intel_ddi_compute_min_voltage(dev_priv, pipe_config);
> +
> return ret;
>
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 32e7cca52da2..83024956a74d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5938,6 +5938,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
>
> dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
> dev_priv->min_cdclk[intel_crtc->pipe] = 0;
> + dev_priv->min_voltage[intel_crtc->pipe] = 0;
> }
>
> /*
> @@ -11304,6 +11305,8 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
> PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
> PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
>
> + PIPE_CONF_CHECK_I(min_voltage);
> +
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> #undef PIPE_CONF_CHECK_P
> @@ -11964,6 +11967,9 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
> intel_state->cdclk.logical.cdclk,
> intel_state->cdclk.actual.cdclk);
> + DRM_DEBUG_KMS("New voltage calculated to be logical %u, actual %u\n",
> + intel_state->cdclk.logical.voltage,
> + intel_state->cdclk.actual.voltage);
> } else {
> to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
> }
> @@ -12532,6 +12538,8 @@ static int intel_atomic_commit(struct drm_device *dev,
> if (intel_state->modeset) {
> memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
> sizeof(intel_state->min_cdclk));
> + memcpy(dev_priv->min_voltage, intel_state->min_voltage,
> + sizeof(intel_state->min_voltage));
> dev_priv->active_crtcs = intel_state->active_crtcs;
> dev_priv->cdclk.logical = intel_state->cdclk.logical;
> dev_priv->cdclk.actual = intel_state->cdclk.actual;
> @@ -15042,6 +15050,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> }
>
> dev_priv->min_cdclk[crtc->pipe] = min_cdclk;
> + dev_priv->min_voltage[crtc->pipe] = crtc_state->min_voltage;
>
> intel_pipe_config_sanity_check(dev_priv, crtc_state);
> }
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 772521440a9f..6c1da88b5fef 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -34,6 +34,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
> struct intel_digital_port *intel_dig_port = intel_mst->primary;
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> @@ -87,6 +88,8 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
>
> pipe_config->dp_m_n.tu = slots;
>
> + intel_ddi_compute_min_voltage(dev_priv, pipe_config);
> +
> return true;
> }
>
> @@ -307,6 +310,8 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
> intel_dp_get_m_n(crtc, pipe_config);
>
> intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
> +
> + intel_ddi_compute_min_voltage(dev_priv, pipe_config);
> }
>
> static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 765a737700c5..002894b13d69 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -386,6 +386,8 @@ struct intel_atomic_state {
> unsigned int active_crtcs;
> /* minimum acceptable cdclk for each pipe */
> int min_cdclk[I915_MAX_PIPES];
> + /* minimum acceptable voltage for each pipe */
> + u8 min_voltage[I915_MAX_PIPES];
>
> struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
>
> @@ -739,6 +741,8 @@ struct intel_crtc_state {
> */
> uint8_t lane_lat_optim_mask;
>
> + u8 min_voltage;
> +
> /* Panel fitter controls for gen2-gen4 + VLV */
> struct {
> u32 control;
> @@ -1294,6 +1298,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
> bool state);
> +void intel_ddi_compute_min_voltage(struct drm_i915_private *dev_priv,
> + struct intel_crtc_state *crtc_state);
> u32 bxt_signal_levels(struct intel_dp *intel_dp);
> uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
> --
> 2.13.6
>
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