On Sun, 15 Jan 2012 01:52:11 +1100 Peter Ross <pross at xvid.org> wrote: > The G35/G45/SandyBridge chipsets expect vertical timings in frame units, > whereas the DRM subsystem uses field units internally for interlaced modes. > > Signed-off-by: Peter Ross <pross at xvid.org> > --- > drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ > 1 files changed, 8 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 2a3f707..ae62f5f 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5316,6 +5316,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > adjusted_mode->crtc_vblank_end -= 1; > adjusted_mode->crtc_vsync_end -= 1; > adjusted_mode->crtc_vsync_start -= 1; > + if (INTEL_INFO(dev)->gen >= 4) { > + adjusted_mode->crtc_vdisplay *= 2; > + adjusted_mode->crtc_vtotal *= 2; > + adjusted_mode->crtc_vblank_start *= 2; > + adjusted_mode->crtc_vblank_end *= 2; > + adjusted_mode->crtc_vsync_end *= 2; > + adjusted_mode->crtc_vsync_start *= 2; > + } > } else > pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */ I *think* this looks ok. It'll only affect pre-ILK chipsets though and interlaced modes. Do we get the ILK+ side right here? I'm with Eugeni; I'd like to see some tested-bys on this, otherwise it looks good. -- Jesse Barnes, Intel Open Source Technology Center -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20120116/0a1fb7d3/attachment.pgp>