On Sat, Jan 14, 2012 at 12:52, Peter Ross <pross at xvid.org> wrote: > This patch set enables enables interlaced mode output on the VGA > and SDVO connectors of the G35 chipset. > > History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220 > > I have tested the changes on an ASUS P5E-VM-HDMI mainboard with VGA > and HDMI CRTs attached. The G45 and SB documentation suggests that > this will also work on those chipsets. (Wording of the vertical > timing registers is near identical). Feedback welcome. > > Peter Ross (2): > drm/i915: specify vertical timings in frame units for interlaced > modes (gen4+) > drm/i915: allow interlaced mode output on the SDVO connector > > drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ > drivers/gpu/drm/i915/intel_sdvo.c | 2 +- > 2 files changed, 9 insertions(+), 1 deletions(-) > I am not very familiar with this area, but both patches look correct to me and are according to the specs as far as I can see. So, for both of them: Reviewed-by: Eugeni Dodonov <eugeni.dodonov at intel.com> Thanks! P.S.: it would be interested to gather some Tested-by's for this though.. -- Eugeni Dodonov <http://eugeni.dodonov.net/> -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20120116/9ba3d2f8/attachment.html>
