Quoting Oscar Mateo (2017-10-13 21:54:03) > Let's try to make sure that all WAs are applied correctly and survive > resumes, resets, etc... (with some help from a companion i-g-t patch). > > v2: > - Rebased > - Print display WAs as well (Ville) > > Signed-off-by: Oscar Mateo <oscar.mateo@xxxxxxxxx> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 53 +++++++++++++++++++++++++++---------- > 1 file changed, 39 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index f108f53..11fb9c3 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -3399,6 +3399,20 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused) > return 0; > } > > +static void check_wa_register(struct seq_file *m, struct i915_wa_reg *wa_reg) > +{ > + struct drm_i915_private *dev_priv = node_to_i915(m->private); > + u32 read; > + bool ok; > + > + read = I915_READ(wa_reg->addr); > + ok = (wa_reg->value & wa_reg->mask) == (read & wa_reg->mask); > + seq_printf(m, "0x%X: 0x%08x, mask: 0x%08x, read: 0x%08x, status: %s\n", > + i915_mmio_reg_offset(wa_reg->addr), > + wa_reg->value, wa_reg->mask, read, > + ok ? "OK" : "FAIL"); > +} > + > static int i915_wa_registers(struct seq_file *m, void *unused) > { > int i; > @@ -3408,6 +3422,7 @@ static int i915_wa_registers(struct seq_file *m, void *unused) > struct drm_device *dev = &dev_priv->drm; > struct i915_workarounds *workarounds = &dev_priv->workarounds; > enum intel_engine_id id; > + u32 whitelist_wa_count = 0; > > ret = mutex_lock_interruptible(&dev->struct_mutex); > if (ret) > @@ -3416,22 +3431,32 @@ static int i915_wa_registers(struct seq_file *m, void *unused) > intel_runtime_pm_get(dev_priv); Grab the forcewake once for everyone. One benefit is that we know then all reads are consistently from the same powercontext epoch (where that matters). -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx