On 10/13/2017 02:42 AM, Sagar Arun Kamble wrote:
On 10/11/2017 12:02 AM, Sujaritha Sundaresan wrote:We currently have two module parameters that control GuC: "enable_guc_loading" and "enable_guc_submission". Whenever we need i915_modparams.enable_guc_submission=1, we also need enable_guc_loading=1.At this point enable_guc_submission parameter is not sanitized. it is sanitized during driver_init_hw that happens post driver_init_early(intel_irq_init). So I think this should be only HAS_GUC.We also need enable_guc_loading=1 when we want to verify the HuC,which is every time we have a HuC (but all platforms with HuC have a GuC and viceversa).v2: Clarifying the commit message (Anusha) v3: Unify seq_puts messages, Re-factoring code as per review (Michal) v4: Rebase v5: Separating message unification into a separate patch v6: Re-factoring code (Sagar, Michal) Rebase Suggested by: Oscar Mateo <oscar.mateo@xxxxxxxxx> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@xxxxxxxxx> Cc: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx> Cc: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> Cc: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> Cc: Oscar Mateo <oscar.mateo@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_debugfs.c | 6 +-- drivers/gpu/drm/i915/i915_drv.h | 9 +++-- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/i915_params.c | 4 -- drivers/gpu/drm/i915/i915_params.h | 1 - drivers/gpu/drm/i915/intel_guc.h | 2 +- drivers/gpu/drm/i915/intel_guc_loader.c | 9 ++--- drivers/gpu/drm/i915/intel_huc.c | 4 +-drivers/gpu/drm/i915/intel_uc.c | 72 +++++++++++++++++----------------drivers/gpu/drm/i915/intel_uncore.c | 3 +- 12 files changed, 59 insertions(+), 57 deletions(-)diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.cindex 9d0c27b..8abc47c 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c@@ -2390,7 +2390,7 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data)struct drm_i915_private *dev_priv = node_to_i915(m->private); struct intel_uc_fw *huc_fw = &dev_priv->huc.fw; - if (!HAS_HUC_UCODE(dev_priv)) + if (!HAS_GUC(dev_priv)) seq_puts(m, "not supported\n"); return 0;@@ -2424,7 +2424,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)struct intel_uc_fw *guc_fw = &dev_priv->guc.fw; u32 tmp, i; - if (!HAS_GUC_UCODE(dev_priv)) + if (!HAS_GUC(dev_priv)) seq_puts(m, "not supported\n"); return 0;@@ -2521,7 +2521,7 @@ static bool check_guc_submission(struct seq_file *m)if (!guc->execbuf_client) { seq_printf(m, "GuC submission %s\n", - HAS_GUC_SCHED(dev_priv) ? + HAS_GUC(dev_priv) ? "disabled" : "not supported"); return false;diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.hindex 770305b..194cbc9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h@@ -3182,9 +3182,12 @@ static inline unsigned int i915_sg_segment_size(void)*/ #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) -#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) -#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) -#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) +#define HAS_GUC_UCODE(dev_priv) ((dev_priv)->guc.fw.path != NULL) +#define HAS_HUC_UCODE(dev_priv) ((dev_priv)->huc.fw.path != NULL) + +#define NEEDS_GUC_LOADING(dev_priv) \ + (HAS_GUC(dev_priv) && \ + (i915_modparams.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.cindex 5bf96a2..692d609 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915, * present or not in use we still need a small bias as ring wraparound* at offset 0 sometimes hangs. No idea why. */ - if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) + if (NEEDS_GUC_LOADING(dev_priv)) ctx->ggtt_offset_bias = GUC_WOPCM_TOP; else ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.cindex 4c60578..b71fd24 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c@@ -3483,7 +3483,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)* currently don't have any bits spare to pass in this upper * restriction! */ - if (HAS_GUC(dev_priv) && i915_modparams.enable_guc_loading) { + if (NEEDS_GUC_LOADING(dev_priv)) { ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);}diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.cindex de77713..19ad4dc 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c@@ -4022,7 +4022,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)for (i = 0; i < MAX_L3_SLICES; ++i) dev_priv->l3_parity.remap_info[i] = NULL; - if (HAS_GUC_SCHED(dev_priv)) + if (NEEDS_GUC_LOADING(dev_priv)) dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
Thanks for pointing this out. I will make the change.
This change can be a new patch and since this/most of the patch is depending on Michal's series I would suggest to post the series once/* Let's track the enabled rps events */diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.cindex b4faeb6..1c25f45 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -162,10 +162,6 @@ struct i915_params i915_modparams __read_mostly = { "(0=use value from vbt [default], 1=low power swing(200mV)," "2=default swing(400mV))"); -i915_param_named_unsafe(enable_guc_loading, int, 0400, - "Enable GuC firmware loading " - "(-1=auto, 0=never [default], 1=if available, 2=required)"); - i915_param_named_unsafe(enable_guc_submission, int, 0400, "Enable GuC submission " "(-1=auto, 0=never [default], 1=if available, 2=required)");diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.hindex c729226..9e1e231 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -44,7 +44,6 @@ param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc_loading, 0) \ param(int, enable_guc_submission, 0) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.hindex aa9a7b5..fa09c2b 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h@@ -103,7 +103,7 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)int intel_guc_resume(struct drm_i915_private *dev_priv);struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);-int intel_guc_select_fw(struct intel_guc *guc); +void intel_guc_select_fw(struct intel_guc *guc); int intel_guc_init_hw(struct intel_guc *guc); u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.cindex c7a800a..cae8333 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -380,9 +380,8 @@ int intel_guc_init_hw(struct intel_guc *guc) * intel_guc_select_fw() - selects GuC firmware for loading * @guc: intel_guc struct * - * Return: zero when we know firmware, non-zero in other casethat gets merged.
Will do.
Can we say option in the message - "Ignoring GuC submission enable option, no hardware"*/ -int intel_guc_select_fw(struct intel_guc *guc) +void intel_guc_select_fw(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); @@ -409,9 +408,9 @@ int intel_guc_select_fw(struct intel_guc *guc) guc->fw.major_ver_wanted = GLK_FW_MAJOR; guc->fw.minor_ver_wanted = GLK_FW_MINOR; } else { - DRM_ERROR("No GuC firmware known for platform with GuC!\n"); - return -ENOENT; + if(HAS_GUC(dev_priv)) + DRM_ERROR("No GUC FW known for a platform with GuC!\n"); + return; } - return 0; }diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.cindex 4b4cf56..7f59c8e 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -175,7 +175,9 @@ void intel_huc_select_fw(struct intel_huc *huc) huc->fw.major_ver_wanted = GLK_HUC_FW_MAJOR; huc->fw.minor_ver_wanted = GLK_HUC_FW_MINOR; } else { - DRM_ERROR("No HuC firmware known for platform with HuC!\n"); + /* For now, everything with a GuC also has a HuC */ + if (HAS_GUC(dev_priv)) + DRM_ERROR("No HuC FW known for a platform with HuC!\n"); return; } }diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.cindex 7b938e8..b687d97 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c@@ -49,45 +49,53 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) { + /* Verify hardware support */ if (!HAS_GUC(dev_priv)) { - if (i915_modparams.enable_guc_loading > 0 || - i915_modparams.enable_guc_submission > 0) - DRM_INFO("Ignoring GuC options, no hardware\n"); - - i915_modparams.enable_guc_loading = 0; - i915_modparams.enable_guc_submission = 0; + if (i915_modparams.enable_guc_submission > 0) + DRM_INFO("Ignoring GuC submission enable, no HW\n");split the message over two lines.
Will do.
+ i915_modparams.enable_guc_submission = 0; return; } - /* A negative value means "use platform default" */ - if (i915_modparams.enable_guc_loading < 0) - i915_modparams.enable_guc_loading = HAS_GUC_UCODE(dev_priv); + /* Verify firmware support */ + if (!HAS_GUC_UCODE(dev_priv)) { + if (i915_modparams.enable_guc_submission == 1) { + DRM_INFO("Ignoring GuC submission enable, no FW\n"); + i915_modparams.enable_guc_submission = 0; + return;this return is not aligned properly. code indentation needs to updated.please run "scripts/checkpatch.pl --strict" on all patches that helps identify such issues faster.
I will check the alignment.
Overall patch logic looks fine. Will need some more updates/rebase later as suggested.+ } - /* Verify firmware version */ - if (i915_modparams.enable_guc_loading) { - if (HAS_HUC_UCODE(dev_priv)) - intel_huc_select_fw(&dev_priv->huc); + if (i915_modparams.enable_guc_submission < 0) { + i915_modparams.enable_guc_submission = 0; + return; + } - if (intel_guc_select_fw(&dev_priv->guc)) - i915_modparams.enable_guc_loading = 0; + /* + * If "required" (> 1), let it continue and we will fail later + * due to the lack of firmware + */ } - /* Can't enable guc submission without guc loaded */ - if (!i915_modparams.enable_guc_loading) - i915_modparams.enable_guc_submission = 0; - - /* A negative value means "use platform default" */ + /*+ * A negative value means "use platform default" (enabled if we have+ * survived to get here) + */ if (i915_modparams.enable_guc_submission < 0) - i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv); + i915_modparams.enable_guc_submission = HAS_GUC(dev_priv); + } void intel_uc_init_early(struct drm_i915_private *dev_priv) { intel_guc_init_early(&dev_priv->guc); + intel_guc_select_fw(&dev_priv->guc); + intel_huc_select_fw(&dev_priv->huc); } void intel_uc_init_fw(struct drm_i915_private *dev_priv) { + if (!HAS_GUC(dev_priv)) + return; intel_uc_fw_fetch(dev_priv, &dev_priv->huc.fw); intel_uc_fw_fetch(dev_priv, &dev_priv->guc.fw); }@@ -154,7 +162,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)struct intel_guc *guc = &dev_priv->guc; int ret, attempts; - if (!i915_modparams.enable_guc_loading) + if (!NEEDS_GUC_LOADING(dev_priv)) return 0; guc_disable_communication(guc);@@ -244,19 +252,15 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)i915_ggtt_disable_guc(dev_priv); DRM_ERROR("GuC init failed\n"); - if (i915_modparams.enable_guc_loading > 1 || - i915_modparams.enable_guc_submission > 1) + if (i915_modparams.enable_guc_submission > 1) { + DRM_NOTE("GuC is required, so marking the GPU as wedged\n"); ret = -EIO; - else - ret = 0; - - if (i915_modparams.enable_guc_submission) { - i915_modparams.enable_guc_submission = 0; + } else if (i915_modparams.enable_guc_submission == 1) {DRM_NOTE("Falling back from GuC submission to execlist mode\n");- } - - i915_modparams.enable_guc_loading = 0; - DRM_NOTE("GuC firmware loading disabled\n"); + i915_modparams.enable_guc_submission = 0; + ret = 0; + } else + ret = 0; return ret; }@@ -265,7 +269,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv){ guc_free_load_err_log(&dev_priv->guc); - if (!i915_modparams.enable_guc_loading) + if (!NEEDS_GUC_LOADING(dev_priv)) return; if (i915_modparams.enable_guc_submission)diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.cindex 983617b..696e11f 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c@@ -1802,8 +1802,7 @@ int intel_guc_reset(struct drm_i915_private *dev_priv){ int ret; - if (!HAS_GUC(dev_priv)) - return -EINVAL; + GEM_BUG_ON(!HAS_GUC(dev_priv)); intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
I will wait for Michal's series before sending the next revision. Thanks for the review. Regards, Sujaritha _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
