On Thu, Oct 12, 2017 at 08:59:20PM +0200, Daniel Vetter wrote:
> On Wed, Oct 11, 2017 at 07:04:47PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > Add a .get_hw_state() method for planes, returning true or false
> > depending on whether the plane is enabled. Use it to rewrite the
> > plane enabled/disabled asserts in platform agnostic fashion.
> >
> > We do lose the pre-gen4 plane<->pipe mapping checks, but since we're
> > supposed sanitize that anyway it doesn't really matter.
> >
> > v2: Reoder patches to not depend on enum old_plane_id
> > Just call assert_plane_disabled() from assert_planes_disabled()
> >
> > Cc: Thierry Reding <thierry.reding@xxxxxxxxx>
> > Cc: Alex Villacís Lasso <alexvillacislasso@xxxxxxxxxxx>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Would have been really nice to pimp our hw state checker (at least for
> synchronous modesets) to verify these. That way I could just blindly trust
> CI.
>
> Anyway, seems correct, but if you can supply such a patch as a follow-up
> would be even better:
Sure, I can at least take a stab a it.
>
> Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 155 +++++++++++++----------------------
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_sprite.c | 43 ++++++++++
> > 3 files changed, 101 insertions(+), 98 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b2c5fba102e1..825ab00b6639 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1192,23 +1192,6 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
> > pipe_name(pipe));
> > }
> >
> > -static void assert_cursor(struct drm_i915_private *dev_priv,
> > - enum pipe pipe, bool state)
> > -{
> > - bool cur_state;
> > -
> > - if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
> > - cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> > - else
> > - cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> > -
> > - I915_STATE_WARN(cur_state != state,
> > - "cursor on pipe %c assertion failure (expected %s, current %s)\n",
> > - pipe_name(pipe), onoff(state), onoff(cur_state));
> > -}
> > -#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
> > -#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
> > -
> > void assert_pipe(struct drm_i915_private *dev_priv,
> > enum pipe pipe, bool state)
> > {
> > @@ -1236,77 +1219,25 @@ void assert_pipe(struct drm_i915_private *dev_priv,
> > pipe_name(pipe), onoff(state), onoff(cur_state));
> > }
> >
> > -static void assert_plane(struct drm_i915_private *dev_priv,
> > - enum plane plane, bool state)
> > +static void assert_plane(struct intel_plane *plane, bool state)
> > {
> > - u32 val;
> > - bool cur_state;
> > + bool cur_state = plane->get_hw_state(plane);
> >
> > - val = I915_READ(DSPCNTR(plane));
> > - cur_state = !!(val & DISPLAY_PLANE_ENABLE);
> > I915_STATE_WARN(cur_state != state,
> > - "plane %c assertion failure (expected %s, current %s)\n",
> > - plane_name(plane), onoff(state), onoff(cur_state));
> > + "%s assertion failure (expected %s, current %s)\n",
> > + plane->base.name, onoff(state), onoff(cur_state));
> > }
> >
> > -#define assert_plane_enabled(d, p) assert_plane(d, p, true)
> > -#define assert_plane_disabled(d, p) assert_plane(d, p, false)
> > +#define assert_plane_enabled(p) assert_plane(p, true)
> > +#define assert_plane_disabled(p) assert_plane(p, false)
> >
> > -static void assert_planes_disabled(struct drm_i915_private *dev_priv,
> > - enum pipe pipe)
> > +static void assert_planes_disabled(struct intel_crtc *crtc)
> > {
> > - int i;
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + struct intel_plane *plane;
> >
> > - /* Primary planes are fixed to pipes on gen4+ */
> > - if (INTEL_GEN(dev_priv) >= 4) {
> > - u32 val = I915_READ(DSPCNTR(pipe));
> > - I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
> > - "plane %c assertion failure, should be disabled but not\n",
> > - plane_name(pipe));
> > - return;
> > - }
> > -
> > - /* Need to check both planes against the pipe */
> > - for_each_pipe(dev_priv, i) {
> > - u32 val = I915_READ(DSPCNTR(i));
> > - enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
> > - DISPPLANE_SEL_PIPE_SHIFT;
> > - I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
> > - "plane %c assertion failure, should be off on pipe %c but is still active\n",
> > - plane_name(i), pipe_name(pipe));
> > - }
> > -}
> > -
> > -static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
> > - enum pipe pipe)
> > -{
> > - int sprite;
> > -
> > - if (INTEL_GEN(dev_priv) >= 9) {
> > - for_each_sprite(dev_priv, pipe, sprite) {
> > - u32 val = I915_READ(PLANE_CTL(pipe, sprite));
> > - I915_STATE_WARN(val & PLANE_CTL_ENABLE,
> > - "plane %d assertion failure, should be off on pipe %c but is still active\n",
> > - sprite, pipe_name(pipe));
> > - }
> > - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > - for_each_sprite(dev_priv, pipe, sprite) {
> > - u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
> > - I915_STATE_WARN(val & SP_ENABLE,
> > - "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> > - sprite_name(pipe, sprite), pipe_name(pipe));
> > - }
> > - } else if (INTEL_GEN(dev_priv) >= 7) {
> > - u32 val = I915_READ(SPRCTL(pipe));
> > - I915_STATE_WARN(val & SPRITE_ENABLE,
> > - "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> > - plane_name(pipe), pipe_name(pipe));
> > - } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
> > - u32 val = I915_READ(DVSCNTR(pipe));
> > - I915_STATE_WARN(val & DVS_ENABLE,
> > - "sprite %c assertion failure, should be off on pipe %c but is still active\n",
> > - plane_name(pipe), pipe_name(pipe));
> > - }
> > + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
> > + assert_plane_disabled(plane);
> > }
> >
> > static void assert_vblank_disabled(struct drm_crtc *crtc)
> > @@ -1899,9 +1830,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
> >
> > DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
> >
> > - assert_planes_disabled(dev_priv, pipe);
> > - assert_cursor_disabled(dev_priv, pipe);
> > - assert_sprites_disabled(dev_priv, pipe);
> > + assert_planes_disabled(crtc);
> >
> > /*
> > * A pipe without a PLL won't actually be able to drive bits from
> > @@ -1971,9 +1900,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
> > * Make sure planes won't keep trying to pump pixels to us,
> > * or we might hang the display.
> > */
> > - assert_planes_disabled(dev_priv, pipe);
> > - assert_cursor_disabled(dev_priv, pipe);
> > - assert_sprites_disabled(dev_priv, pipe);
> > + assert_planes_disabled(crtc);
> >
> > reg = PIPECONF(cpu_transcoder);
> > val = I915_READ(reg);
> > @@ -3370,6 +3297,14 @@ static void i9xx_disable_primary_plane(struct intel_plane *primary,
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > }
> >
> > +static bool i9xx_plane_get_hw_state(struct intel_plane *primary)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> > + enum plane plane = primary->plane;
> > +
> > + return I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE;
> > +}
> > +
> > static u32
> > intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
> > {
> > @@ -3638,6 +3573,15 @@ static void skylake_disable_primary_plane(struct intel_plane *primary,
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > }
> >
> > +static bool skylake_primary_get_hw_state(struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum pipe pipe = plane->pipe;
> > + enum plane_id plane_id = plane->id;
> > +
> > + return I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
> > +}
> > +
> > static int
> > __intel_display_resume(struct drm_device *dev,
> > struct drm_atomic_state *state,
> > @@ -4944,7 +4888,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> > * a vblank wait.
> > */
> >
> > - assert_plane_enabled(dev_priv, crtc->plane);
> > + assert_plane_enabled(to_intel_plane(crtc->base.primary));
> > +
> > if (IS_BROADWELL(dev_priv)) {
> > mutex_lock(&dev_priv->pcu_lock);
> > WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> > @@ -4977,7 +4922,8 @@ void hsw_disable_ips(struct intel_crtc *crtc)
> > if (!crtc->config->ips_enabled)
> > return;
> >
> > - assert_plane_enabled(dev_priv, crtc->plane);
> > + assert_plane_enabled(to_intel_plane(crtc->base.primary));
> > +
> > if (IS_BROADWELL(dev_priv)) {
> > mutex_lock(&dev_priv->pcu_lock);
> > WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> > @@ -9557,6 +9503,13 @@ static void i845_disable_cursor(struct intel_plane *plane,
> > i845_update_cursor(plane, NULL, NULL);
> > }
> >
> > +static bool i845_cursor_get_hw_state(struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +
> > + return I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> > +}
> > +
> > static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -9750,6 +9703,13 @@ static void i9xx_disable_cursor(struct intel_plane *plane,
> > i9xx_update_cursor(plane, NULL, NULL);
> > }
> >
> > +static bool i9xx_cursor_get_hw_state(struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum pipe pipe = plane->pipe;
> > +
> > + return I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> > +}
> >
> > /* VESA 640x480x72Hz mode to set on the pipe */
> > static const struct drm_display_mode load_detect_mode = {
> > @@ -13235,6 +13195,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >
> > primary->update_plane = skylake_update_primary_plane;
> > primary->disable_plane = skylake_disable_primary_plane;
> > + primary->get_hw_state = skylake_primary_get_hw_state;
> > } else if (INTEL_GEN(dev_priv) >= 9) {
> > intel_primary_formats = skl_primary_formats;
> > num_formats = ARRAY_SIZE(skl_primary_formats);
> > @@ -13245,6 +13206,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >
> > primary->update_plane = skylake_update_primary_plane;
> > primary->disable_plane = skylake_disable_primary_plane;
> > + primary->get_hw_state = skylake_primary_get_hw_state;
> > } else if (INTEL_GEN(dev_priv) >= 4) {
> > intel_primary_formats = i965_primary_formats;
> > num_formats = ARRAY_SIZE(i965_primary_formats);
> > @@ -13252,6 +13214,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >
> > primary->update_plane = i9xx_update_primary_plane;
> > primary->disable_plane = i9xx_disable_primary_plane;
> > + primary->get_hw_state = i9xx_plane_get_hw_state;
> > } else {
> > intel_primary_formats = i8xx_primary_formats;
> > num_formats = ARRAY_SIZE(i8xx_primary_formats);
> > @@ -13259,6 +13222,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> >
> > primary->update_plane = i9xx_update_primary_plane;
> > primary->disable_plane = i9xx_disable_primary_plane;
> > + primary->get_hw_state = i9xx_plane_get_hw_state;
> > }
> >
> > if (INTEL_GEN(dev_priv) >= 9)
> > @@ -13348,10 +13312,12 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> > cursor->update_plane = i845_update_cursor;
> > cursor->disable_plane = i845_disable_cursor;
> > + cursor->get_hw_state = i845_cursor_get_hw_state;
> > cursor->check_plane = i845_check_cursor;
> > } else {
> > cursor->update_plane = i9xx_update_cursor;
> > cursor->disable_plane = i9xx_disable_cursor;
> > + cursor->get_hw_state = i9xx_cursor_get_hw_state;
> > cursor->check_plane = i9xx_check_cursor;
> > }
> >
> > @@ -14699,8 +14665,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> > DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
> > pipe_name(pipe));
> >
> > - assert_plane_disabled(dev_priv, PLANE_A);
> > - assert_plane_disabled(dev_priv, PLANE_B);
> > + assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A));
> > + assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B));
> >
> > I915_WRITE(PIPECONF(pipe), 0);
> > POSTING_READ(PIPECONF(pipe));
> > @@ -14914,20 +14880,13 @@ void i915_redisable_vga(struct drm_i915_private *dev_priv)
> > intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
> > }
> >
> > -static bool primary_get_hw_state(struct intel_plane *plane)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > -
> > - return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
> > -}
> > -
> > /* FIXME read out full plane state for all planes */
> > static void readout_plane_state(struct intel_crtc *crtc)
> > {
> > struct intel_plane *primary = to_intel_plane(crtc->base.primary);
> > bool visible;
> >
> > - visible = crtc->active && primary_get_hw_state(primary);
> > + visible = crtc->active && primary->get_hw_state(primary);
> >
> > intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
> > to_intel_plane_state(primary->base.state),
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index cdda0a84babe..24bbf0518473 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -868,6 +868,7 @@ struct intel_plane {
> > const struct intel_plane_state *plane_state);
> > void (*disable_plane)(struct intel_plane *plane,
> > struct intel_crtc *crtc);
> > + bool (*get_hw_state)(struct intel_plane *plane);
> > int (*check_plane)(struct intel_plane *plane,
> > struct intel_crtc_state *crtc_state,
> > struct intel_plane_state *state);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index f29369622d2c..a533df6fe706 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -329,6 +329,16 @@ skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > }
> >
> > +static bool
> > +skl_plane_get_hw_state(struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum plane_id plane_id = plane->id;
> > + enum pipe pipe = plane->pipe;
> > +
> > + return I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
> > +}
> > +
> > static void
> > chv_update_csc(struct intel_plane *plane, uint32_t format)
> > {
> > @@ -506,6 +516,16 @@ vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > }
> >
> > +static bool
> > +vlv_plane_get_hw_state(struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum plane_id plane_id = plane->id;
> > + enum pipe pipe = plane->pipe;
> > +
> > + return I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
> > +}
> > +
> > static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -646,6 +666,15 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > }
> >
> > +static bool
> > +ivb_plane_get_hw_state(struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum pipe pipe = plane->pipe;
> > +
> > + return I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
> > +}
> > +
> > static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -777,6 +806,15 @@ g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
> > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> > }
> >
> > +static bool
> > +g4x_plane_get_hw_state(struct intel_plane *plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum pipe pipe = plane->pipe;
> > +
> > + return I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
> > +}
> > +
> > static int
> > intel_check_sprite_plane(struct intel_plane *plane,
> > struct intel_crtc_state *crtc_state,
> > @@ -1232,6 +1270,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >
> > intel_plane->update_plane = skl_update_plane;
> > intel_plane->disable_plane = skl_disable_plane;
> > + intel_plane->get_hw_state = skl_plane_get_hw_state;
> >
> > plane_formats = skl_plane_formats;
> > num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> > @@ -1242,6 +1281,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >
> > intel_plane->update_plane = skl_update_plane;
> > intel_plane->disable_plane = skl_disable_plane;
> > + intel_plane->get_hw_state = skl_plane_get_hw_state;
> >
> > plane_formats = skl_plane_formats;
> > num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> > @@ -1252,6 +1292,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >
> > intel_plane->update_plane = vlv_update_plane;
> > intel_plane->disable_plane = vlv_disable_plane;
> > + intel_plane->get_hw_state = vlv_plane_get_hw_state;
> >
> > plane_formats = vlv_plane_formats;
> > num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> > @@ -1267,6 +1308,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >
> > intel_plane->update_plane = ivb_update_plane;
> > intel_plane->disable_plane = ivb_disable_plane;
> > + intel_plane->get_hw_state = ivb_plane_get_hw_state;
> >
> > plane_formats = snb_plane_formats;
> > num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> > @@ -1277,6 +1319,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >
> > intel_plane->update_plane = g4x_update_plane;
> > intel_plane->disable_plane = g4x_disable_plane;
> > + intel_plane->get_hw_state = g4x_plane_get_hw_state;
> >
> > modifiers = i9xx_plane_format_modifiers;
> > if (IS_GEN6(dev_priv)) {
> > --
> > 2.13.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
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