Re: [PATCH 5/9] drm/i915: Cleanup enum pipe/enum plane_id/enum old_plane_id in initial fb readout

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On Wed, Oct 11, 2017 at 07:04:51PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> 
> Use enum pipe, enum plane_id, and enum old_plane_id consistently in the
> initial framebuffe readout.
> 
> v2: Use old_plane_id in the ilk code
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>

I didn't check whether you caught them all, but I hope someone with the
pain tolerance to compile the kernel with clang with catch those :-)

Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 58 ++++++++++++++++++++----------------
>  1 file changed, 32 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9d37c758f7b5..21160a06ab36 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7456,14 +7456,16 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	enum old_plane_id plane_id = plane->plane;
> +	enum pipe pipe = crtc->pipe;
>  	u32 val, base, offset;
> -	int pipe = crtc->pipe, plane = crtc->plane;
>  	int fourcc, pixel_format;
>  	unsigned int aligned_height;
>  	struct drm_framebuffer *fb;
>  	struct intel_framebuffer *intel_fb;
>  
> -	val = I915_READ(DSPCNTR(plane));
> +	val = I915_READ(DSPCNTR(plane_id));
>  	if (!(val & DISPLAY_PLANE_ENABLE))
>  		return;
>  
> @@ -7490,12 +7492,12 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	if (INTEL_GEN(dev_priv) >= 4) {
>  		if (plane_config->tiling)
> -			offset = I915_READ(DSPTILEOFF(plane));
> +			offset = I915_READ(DSPTILEOFF(plane_id));
>  		else
> -			offset = I915_READ(DSPLINOFF(plane));
> -		base = I915_READ(DSPSURF(plane)) & 0xfffff000;
> +			offset = I915_READ(DSPLINOFF(plane_id));
> +		base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
>  	} else {
> -		base = I915_READ(DSPADDR(plane));
> +		base = I915_READ(DSPADDR(plane_id));
>  	}
>  	plane_config->base = base;
>  
> @@ -7503,15 +7505,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>  	fb->width = ((val >> 16) & 0xfff) + 1;
>  	fb->height = ((val >> 0) & 0xfff) + 1;
>  
> -	val = I915_READ(DSPSTRIDE(pipe));
> +	val = I915_READ(DSPSTRIDE(plane_id));
>  	fb->pitches[0] = val & 0xffffffc0;
>  
>  	aligned_height = intel_fb_align_height(fb, 0, fb->height);
>  
>  	plane_config->size = fb->pitches[0] * aligned_height;
>  
> -	DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> -		      pipe_name(pipe), plane, fb->width, fb->height,
> +	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> +		      crtc->base.name, plane->base.name, fb->width, fb->height,
>  		      fb->format->cpp[0] * 8, base, fb->pitches[0],
>  		      plane_config->size);
>  
> @@ -8482,8 +8484,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	enum plane_id plane_id = plane->id;
> +	enum pipe pipe = crtc->pipe;
>  	u32 val, base, offset, stride_mult, tiling;
> -	int pipe = crtc->pipe;
>  	int fourcc, pixel_format;
>  	unsigned int aligned_height;
>  	struct drm_framebuffer *fb;
> @@ -8499,7 +8503,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	fb->dev = dev;
>  
> -	val = I915_READ(PLANE_CTL(pipe, 0));
> +	val = I915_READ(PLANE_CTL(pipe, plane_id));
>  	if (!(val & PLANE_CTL_ENABLE))
>  		goto error;
>  
> @@ -8535,16 +8539,16 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  		goto error;
>  	}
>  
> -	base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
> +	base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
>  	plane_config->base = base;
>  
> -	offset = I915_READ(PLANE_OFFSET(pipe, 0));
> +	offset = I915_READ(PLANE_OFFSET(pipe, plane_id));
>  
> -	val = I915_READ(PLANE_SIZE(pipe, 0));
> +	val = I915_READ(PLANE_SIZE(pipe, plane_id));
>  	fb->height = ((val >> 16) & 0xfff) + 1;
>  	fb->width = ((val >> 0) & 0x1fff) + 1;
>  
> -	val = I915_READ(PLANE_STRIDE(pipe, 0));
> +	val = I915_READ(PLANE_STRIDE(pipe, plane_id));
>  	stride_mult = intel_fb_stride_alignment(fb, 0);
>  	fb->pitches[0] = (val & 0x3ff) * stride_mult;
>  
> @@ -8552,8 +8556,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
>  
>  	plane_config->size = fb->pitches[0] * aligned_height;
>  
> -	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> -		      pipe_name(pipe), fb->width, fb->height,
> +	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> +		      crtc->base.name, plane->base.name, fb->width, fb->height,
>  		      fb->format->cpp[0] * 8, base, fb->pitches[0],
>  		      plane_config->size);
>  
> @@ -8594,14 +8598,16 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	enum old_plane_id plane_id = plane->plane;
> +	enum pipe pipe = crtc->pipe;
>  	u32 val, base, offset;
> -	int pipe = crtc->pipe;
>  	int fourcc, pixel_format;
>  	unsigned int aligned_height;
>  	struct drm_framebuffer *fb;
>  	struct intel_framebuffer *intel_fb;
>  
> -	val = I915_READ(DSPCNTR(pipe));
> +	val = I915_READ(DSPCNTR(plane_id));
>  	if (!(val & DISPLAY_PLANE_ENABLE))
>  		return;
>  
> @@ -8626,14 +8632,14 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
>  	fourcc = i9xx_format_to_fourcc(pixel_format);
>  	fb->format = drm_format_info(fourcc);
>  
> -	base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
> +	base = I915_READ(DSPSURF(plane_id)) & 0xfffff000;
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		offset = I915_READ(DSPOFFSET(pipe));
> +		offset = I915_READ(DSPOFFSET(plane_id));
>  	} else {
>  		if (plane_config->tiling)
> -			offset = I915_READ(DSPTILEOFF(pipe));
> +			offset = I915_READ(DSPTILEOFF(plane_id));
>  		else
> -			offset = I915_READ(DSPLINOFF(pipe));
> +			offset = I915_READ(DSPLINOFF(plane_id));
>  	}
>  	plane_config->base = base;
>  
> @@ -8641,15 +8647,15 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
>  	fb->width = ((val >> 16) & 0xfff) + 1;
>  	fb->height = ((val >> 0) & 0xfff) + 1;
>  
> -	val = I915_READ(DSPSTRIDE(pipe));
> +	val = I915_READ(DSPSTRIDE(plane_id));
>  	fb->pitches[0] = val & 0xffffffc0;
>  
>  	aligned_height = intel_fb_align_height(fb, 0, fb->height);
>  
>  	plane_config->size = fb->pitches[0] * aligned_height;
>  
> -	DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> -		      pipe_name(pipe), fb->width, fb->height,
> +	DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
> +		      crtc->base.name, plane->base.name, fb->width, fb->height,
>  		      fb->format->cpp[0] * 8, base, fb->pitches[0],
>  		      plane_config->size);
>  
> -- 
> 2.13.6
> 
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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