Re: [CI] drm/i915: Use a cached mapping for the physical HWS

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On 11/10/17 14:43, Chris Wilson wrote:
Quoting Chris Wilson (2017-10-11 12:21:06)
Older gen use a physical address for the hardware status page, for which
we use cache-coherent writes. As the writes are into the cpu cache, we use
a normal WB mapped page to read the HWS, used for our seqno tracking.

Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
which so far have not reoccurred with this patch. How reliable that
evidence is remains to be seen.

v2: Explicitly pass the expected physical address to the hw
v3: Also remember the wild writes we once had for HWS above 4G.

Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Daniel Vetter <daniel@xxxxxxxx>
Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>

Oops, dropped the grumpy r-b from Daniel.

I was just wanting to see if this helped gdg, but I just remembered CI
doesn't include gdg in BAT.

Tomi, still an issue as it's reasonably stable now?

There hasn't been recent hangs for GDG, so I added it to Patchwork and Trybot runs.

Tomi
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