With GuC based SLPC, frequency control will be moved to GuC and Host will continue to control RC6 and LLC ring frequency setup. This needs separate handling of RPS, RC6 and LLC ring frequencies in i915 flows. We still continue use the *gt_powersave routines with separate status variables for RPS, RC6, ring frequency as pm.rps.enabled, pm.rc6.enabled and pm.llc_pstate.configured respectively in dev_priv. Post this, with SLPC changes integrated we can just skip the Host RPS path in i915 PM flows. v2: Added new patch 2. Addressed review comments. Pending review for last 3 patches and patch 2 currently. v3: Fixed checkpatch issue in patch 1. Updated patch 6 with new name for i915_runtime_pm structure variable as runtime_pm. Added new patch 7 to move hw_lock out of rps structure. Updated patch 8 to name rc6/rps/ring state as gt_pm. Updated patch 10 to change the llc pstate enable disable function names. Removed WARN_ON for pcu_lock from lower level functions in patch 11. Also addressed review comments on patch 12. Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Cc: Imre Deak <imre.deak@xxxxxxxxx> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@xxxxxxxxx> Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> Cc: Beuchat, Marc <marc.beuchat@xxxxxxxxx> Sagar Arun Kamble (12): drm/i915: Separate RPS and RC6 handling for gen6+ drm/i915: Remove superfluous IS_BDW checks and non-BDW changes from gen8_enable_rps drm/i915: Separate RPS and RC6 handling for BDW drm/i915: Separate RPS and RC6 handling for VLV drm/i915: Separate RPS and RC6 handling for CHV drm/i915: Name i915_runtime_pm structure in dev_priv as "runtime_pm" drm/i915: Move rps.hw_lock to dev_priv and s/hw_lock/pcu_lock drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "gt_pm" drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled drm/i915: Create generic function to setup LLC ring frequency table drm/i915: Create generic functions to control RC6, RPS drm/i915: Introduce separate status variable for RC6 and LLC ring frequency setup drivers/gpu/drm/i915/i915_debugfs.c | 164 +++---- drivers/gpu/drm/i915/i915_drv.c | 10 +- drivers/gpu/drm/i915/i915_drv.h | 40 +- drivers/gpu/drm/i915/i915_gem.c | 21 +- drivers/gpu/drm/i915/i915_gem_request.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 +- drivers/gpu/drm/i915/i915_guc_submission.c | 10 +- drivers/gpu/drm/i915/i915_irq.c | 99 +++-- drivers/gpu/drm/i915/i915_sysfs.c | 76 ++-- drivers/gpu/drm/i915/intel_cdclk.c | 40 +- drivers/gpu/drm/i915/intel_display.c | 12 +- drivers/gpu/drm/i915/intel_drv.h | 14 +- drivers/gpu/drm/i915/intel_guc.c | 3 +- drivers/gpu/drm/i915/intel_pm.c | 666 +++++++++++++++++------------ drivers/gpu/drm/i915/intel_runtime_pm.c | 26 +- drivers/gpu/drm/i915/intel_sideband.c | 6 +- 16 files changed, 678 insertions(+), 515 deletions(-) -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx