WaSendPushConstantsFromMMIO: "If not using RS, we must send two
MMIO registers at context create to trigger push constants at
3D primitive"
There is almost no documentation on Spec or wa_database about
this WaSendPushConstantsFromMMIO. So we also found out in another
place that WaSendPushConstantsFromMMIO was only adding
COMMON_SLICE_CHICKEN2 in a white list.
So we looked to the programming notes of COMMON_SLICE_CHICKEN2
and we notice that this bit 12 is marked in association with
2 other MMIO registers for SKL+. Apparently for SKL+ we should
check few MMIOs to decide for set or reset of this bit 12.
Also "gather" is related to gather and packing of constants elements
into "push constants".
Mesa has no plans of using RS so there is no need to whitelist
and we only need to initialize the context image with that bit clear.
v2: Move to cnl_init_workarounds as Chris suggested.
Add both Wa names and improve commit message as Rafael suggested.
Cc: Rafael Antognolli <rafael.antognolli@xxxxxxxxx>
Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 807a7aafc089..3beb7d327785 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1296,6 +1296,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
+ /* WaDisableGatherAtSetShaderCommonSlice:cnl */
+ /* WaSendPushConstantsFromMMIO:cnl */
+ WA_CLR_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
+
/* WaInPlaceDecompressionHang:cnl */
I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
(I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
--
2.13.5
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