Quoting Sagar Arun Kamble (2017-10-04 15:07:17) > This patch separates RC6 and RPS enabling for BDW. > RC6/RPS Disabling are handled through gen6 functions. > PM Programming guide recommends a sequence within forcewakes to > configure RC6, RPS and ring frequencies in sequence. With this > patch the order is still maintained. > > v2: Update sequence numbers in RC6 programming and comment about > intent of reset_rps during gen8_enable_rps. (Radoslaw) > > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> > Cc: Imre Deak <imre.deak@xxxxxxxxx> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@xxxxxxxxx> > --- > @@ -6645,16 +6645,18 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv) > if (intel_enable_rc6() & INTEL_RC6_ENABLE) > rc6_mask = GEN6_RC_CTL_RC6_ENABLE; > intel_print_rc6_info(dev_priv, rc6_mask); > - if (IS_BROADWELL(dev_priv)) > - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | > - GEN7_RC_CTL_TO_MODE | > - rc6_mask); > - else > - I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | > - GEN6_RC_CTL_EI_MODE(1) | > - rc6_mask); > + I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | > + GEN7_RC_CTL_TO_MODE | > + rc6_mask); Ah, presumably you noted that this function is only called for bdw. Please make this a separate patch, and fixup the earlier IS_BROADWELL as well. The rest of the patch makes sense, Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
