Re: [PATCH v5 3/5] drm/i915/guc: Move GuC core definitions into dedicated files

[Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>]

On 10/4/2017 11:43 PM, Michal Wajdeczko wrote:
> Move GuC core definitions into dedicated files as we want to
> keep GuC specific code in separated files.
>
> v2: move all functions in single patch (Joonas)
>      fix old checkpatch issues (Sagar)
>
> v3: rebased
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx>
> Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> #1
> ---
<snip>
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> new file mode 100644
> index 0000000..094d649
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -0,0 +1,109 @@
> +/*
> + * Copyright © 2014-2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef _INTEL_GUC_H_
> +#define _INTEL_GUC_H_
> +
> +#include "intel_uncore.h"
> +#include "intel_guc_fwif.h"
> +#include "intel_guc_ct.h"
> +#include "intel_guc_log.h"
> +#include "intel_uc_fw.h"
> +#include "i915_guc_reg.h"
> +#include "i915_vma.h"
> +
> +struct intel_guc {
> +	struct intel_uc_fw fw;
> +	struct intel_guc_log log;
> +	struct intel_guc_ct ct;
> +
> +	/* Log snapshot if GuC errors during load */
> +	struct drm_i915_gem_object *load_err_log;
> +
> +	/* intel_guc_recv interrupt related state */
> +	bool interrupts_enabled;
> +
> +	struct i915_vma *ads_vma;
> +	struct i915_vma *stage_desc_pool;
> +	void *stage_desc_pool_vaddr;
> +	struct ida stage_ids;
> +
> +	struct i915_guc_client *execbuf_client;
> +
> +	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
> +	uint32_t db_cacheline;		/* Cyclic counter mod pagesize	*/
> +
> +	/* GuC's FW specific registers used in MMIO send */
> +	struct {
> +		u32 base;
> +		unsigned int count;
> +		enum forcewake_domains fw_domains;
> +	} send_regs;
> +
> +	/* To serialize the intel_guc_send actions */
> +	struct mutex send_mutex;
> +
> +	/* GuC's FW specific send function */
> +	int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
> +
> +	/* GuC's FW specific notify function */
> +	void (*notify)(struct intel_guc *guc);
> +};
> +
> +static
> +inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
> +{
> +	return guc->send(guc, action, len);
> +}
> +
> +static inline void intel_guc_notify(struct intel_guc *guc)
> +{
> +	guc->notify(guc);
> +}
> +
> +static inline u32 guc_ggtt_offset(struct i915_vma *vma)
> +{
> +	u32 offset = i915_ggtt_offset(vma);
> +
> +	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
> +	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
> +
> +	return offset;
> +}
> +
> +void intel_guc_init_early(struct intel_guc *guc);
> +void intel_guc_init_send_regs(struct intel_guc *guc);
> +int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
> +int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
> +int intel_guc_sample_forcewake(struct intel_guc *guc);
> +int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
> +int intel_guc_suspend(struct drm_i915_private *dev_priv);
> +int intel_guc_resume(struct drm_i915_private *dev_priv);
> +struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
> +
/* intel_guc_loader.c */ was dropped.
> +int intel_guc_select_fw(struct intel_guc *guc);
> +int intel_guc_init_hw(struct intel_guc *guc);
> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 770bac4..cb9f13f 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -82,25 +82,9 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
>   		i915_modparams.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
>   }
>   
> -static void gen8_guc_raise_irq(struct intel_guc *guc)
> -{
> -	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -
> -	I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
> -}
> -
> -static void guc_init_early(struct intel_guc *guc)
> -{
> -	intel_guc_ct_init_early(&guc->ct);
> -
> -	mutex_init(&guc->send_mutex);
> -	guc->send = intel_guc_send_nop;
> -	guc->notify = gen8_guc_raise_irq;
> -}
> -
>   void intel_uc_init_early(struct drm_i915_private *dev_priv)
>   {
> -	guc_init_early(&dev_priv->guc);
> +	intel_guc_init_early(&dev_priv->guc);
>   }
>   
>   void intel_uc_init_fw(struct drm_i915_private *dev_priv)
> @@ -115,32 +99,6 @@ void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
>   	intel_uc_fw_fini(&dev_priv->huc.fw);
>   }
>   
> -static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
> -{
> -	GEM_BUG_ON(!guc->send_regs.base);
> -	GEM_BUG_ON(!guc->send_regs.count);
> -	GEM_BUG_ON(i >= guc->send_regs.count);
> -
> -	return _MMIO(guc->send_regs.base + 4 * i);
> -}
> -
> -static void guc_init_send_regs(struct intel_guc *guc)
> -{
> -	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	enum forcewake_domains fw_domains = 0;
> -	unsigned int i;
> -
> -	guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> -	guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
> -
> -	for (i = 0; i < guc->send_regs.count; i++) {
> -		fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
> -					guc_send_reg(guc, i),
> -					FW_REG_READ | FW_REG_WRITE);
> -	}
> -	guc->send_regs.fw_domains = fw_domains;
> -}
> -
>   /**
>    * intel_uc_init_mmio - setup uC MMIO access
>    *
> @@ -151,7 +109,7 @@ static void guc_init_send_regs(struct intel_guc *guc)
>    */
>   void intel_uc_init_mmio(struct drm_i915_private *dev_priv)
>   {
> -	guc_init_send_regs(&dev_priv->guc);
> +	intel_guc_init_send_regs(&dev_priv->guc);
>   }
>   
>   static void guc_capture_load_err_log(struct intel_guc *guc)
> @@ -192,27 +150,6 @@ static void guc_disable_communication(struct intel_guc *guc)
>   	guc->send = intel_guc_send_nop;
>   }
>   
> -/**
> - * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
> - * @guc: intel_guc structure
> - * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
> - *
> - * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
> - * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
> - * intel_huc_auth().
> - *
> - * Return:	non-zero code on error
> - */
> -int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
> -{
> -	u32 action[] = {
> -		INTEL_GUC_ACTION_AUTHENTICATE_HUC,
> -		rsa_offset
> -	};
> -
> -	return intel_guc_send(guc, action, ARRAY_SIZE(action));
> -}
> -
>   int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>   {
>   	struct intel_guc *guc = &dev_priv->guc;
> @@ -344,82 +281,3 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
>   
>   	i915_ggtt_disable_guc(dev_priv);
>   }
> -
> -int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
> -{
> -	WARN(1, "Unexpected send: action=%#x\n", *action);
> -	return -ENODEV;
> -}
> -
> -/*
> - * This function implements the MMIO based host to GuC interface.
> - */
> -int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
> -{
> -	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	u32 status;
> -	int i;
> -	int ret;
> -
> -	GEM_BUG_ON(!len);
> -	GEM_BUG_ON(len > guc->send_regs.count);
> -
> -	/* If CT is available, we expect to use MMIO only during init/fini */
> -	GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
> -		*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
> -		*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
> -
> -	mutex_lock(&guc->send_mutex);
> -	intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
> -
> -	for (i = 0; i < len; i++)
> -		I915_WRITE(guc_send_reg(guc, i), action[i]);
> -
> -	POSTING_READ(guc_send_reg(guc, i - 1));
> -
> -	intel_guc_notify(guc);
> -
> -	/*
> -	 * No GuC command should ever take longer than 10ms.
> -	 * Fast commands should still complete in 10us.
> -	 */
> -	ret = __intel_wait_for_register_fw(dev_priv,
> -					   guc_send_reg(guc, 0),
> -					   INTEL_GUC_RECV_MASK,
> -					   INTEL_GUC_RECV_MASK,
> -					   10, 10, &status);
> -	if (status != INTEL_GUC_STATUS_SUCCESS) {
> -		/*
> -		 * Either the GuC explicitly returned an error (which
> -		 * we convert to -EIO here) or no response at all was
> -		 * received within the timeout limit (-ETIMEDOUT)
> -		 */
> -		if (ret != -ETIMEDOUT)
> -			ret = -EIO;
> -
> -		DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
> -			 " ret=%d status=0x%08X response=0x%08X\n",
> -			 action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
> -	}
> -
> -	intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
> -	mutex_unlock(&guc->send_mutex);
> -
> -	return ret;
> -}
> -
> -int intel_guc_sample_forcewake(struct intel_guc *guc)
> -{
> -	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -	u32 action[2];
> -
> -	action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
> -	/* WaRsDisableCoarsePowerGating:skl,bxt */
> -	if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
> -		action[1] = 0;
> -	else
> -		/* bit 0 and 1 are for Render and Media domain separately */
> -		action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
> -
> -	return intel_guc_send(guc, action, ARRAY_SIZE(action));
> -}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 2f741a9..e18d3bb 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -24,54 +24,9 @@
>   #ifndef _INTEL_UC_H_
>   #define _INTEL_UC_H_
>   
> -#include "intel_uc_fw.h"
> -#include "intel_guc_fwif.h"
> -#include "i915_guc_reg.h"
> -#include "intel_ringbuffer.h"
> -#include "intel_guc_ct.h"
> -#include "intel_guc_log.h"
> -#include "i915_vma.h"
> +#include "intel_guc.h"
>   #include "intel_huc.h"
>   
> -struct intel_guc {
> -	struct intel_uc_fw fw;
> -	struct intel_guc_log log;
> -	struct intel_guc_ct ct;
> -
> -	/* Log snapshot if GuC errors during load */
> -	struct drm_i915_gem_object *load_err_log;
> -
> -	/* intel_guc_recv interrupt related state */
> -	bool interrupts_enabled;
> -
> -	struct i915_vma *ads_vma;
> -	struct i915_vma *stage_desc_pool;
> -	void *stage_desc_pool_vaddr;
> -	struct ida stage_ids;
> -
> -	struct i915_guc_client *execbuf_client;
> -
> -	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
> -	uint32_t db_cacheline;		/* Cyclic counter mod pagesize	*/
> -
> -	/* GuC's FW specific registers used in MMIO send */
> -	struct {
> -		u32 base;
> -		unsigned int count;
> -		enum forcewake_domains fw_domains;
> -	} send_regs;
> -
> -	/* To serialize the intel_guc_send actions */
> -	struct mutex send_mutex;
> -
> -	/* GuC's FW specific send function */
> -	int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
> -
> -	/* GuC's FW specific notify function */
> -	void (*notify)(struct intel_guc *guc);
> -};
> -
> -/* intel_uc.c */
>   void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
>   void intel_uc_init_early(struct drm_i915_private *dev_priv);
>   void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
> @@ -79,36 +34,5 @@ void intel_uc_init_fw(struct drm_i915_private *dev_priv);
>   void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
>   int intel_uc_init_hw(struct drm_i915_private *dev_priv);
>   void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
> -int intel_guc_sample_forcewake(struct intel_guc *guc);
> -int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
> -int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
> -int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
> -
> -static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
> -{
> -	return guc->send(guc, action, len);
> -}
> -
> -static inline void intel_guc_notify(struct intel_guc *guc)
> -{
> -	guc->notify(guc);
> -}
> -
> -/* intel_guc_loader.c */
> -int intel_guc_select_fw(struct intel_guc *guc);
> -int intel_guc_init_hw(struct intel_guc *guc);
> -int intel_guc_suspend(struct drm_i915_private *dev_priv);
> -int intel_guc_resume(struct drm_i915_private *dev_priv);
> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
> -
> -struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
> -
> -static inline u32 guc_ggtt_offset(struct i915_vma *vma)
> -{
> -	u32 offset = i915_ggtt_offset(vma);
> -	GEM_BUG_ON(offset < GUC_WOPCM_TOP);
> -	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
> -	return offset;
> -}
>   
>   #endif

_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx