Quoting Lionel Landwerlin (2017-10-04 14:51:18) > On 04/10/17 14:05, Matthew Auld wrote: > > On 4 October 2017 at 13:43, Lionel Landwerlin > > <lionel.g.landwerlin@xxxxxxxxx> wrote: > >> On 04/10/17 12:46, Matthew Auld wrote: > >>> On 4 October 2017 at 12:19, Lionel Landwerlin > >>> <lionel.g.landwerlin@xxxxxxxxx> wrote: > >>>> From: Robert Bragg <robert@xxxxxxxxxxxxx> > >>>> > >>>> Signed-off-by: Robert Bragg <robert@xxxxxxxxxxxxx> > >>>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx> > > <SNIP> > > > >>>> + bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", > >>>> 4096, 64); > >>> alignment=64 ? > >> > >> Alignment requirement for MI_RPC are lower than with surfaces and indeed > >> 64bytes. > > The minimum gtt alignment is 4K, so specifying 64bytes doesn't make sense. > > > Same can be said about an allocation of 4096 with alignement of 4096. > > I can send a fix to set all of those to 0. It still has some merit as pure documentation, even if it will be converted to an alignment of 0 by the kernel. That will be useful if instead of allocating a whole bo, you wish to do suballocations. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
