On Wed, 2017-09-27 at 17:44 +0100, Chris Wilson wrote: > From: Jeff McGee <jeff.mcgee@xxxxxxxxx> > > The WA applies to all production Gen9 and requires both enabling and > whitelisting of the per-context preemption control register. > > Signed-off-by: Jeff McGee <jeff.mcgee@xxxxxxxxx> > Signed-off-by: Michał Winiarski <michal.winiarski@xxxxxxxxx> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> <SNIP> > --- > drivers/gpu/drm/i915/intel_engine_cs.c | 12 +++--------- > 1 file changed, 3 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index a28e2a864cf1..af3fe494a429 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1077,7 +1077,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > return ret; > > /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */ To have the record correct, this applies to CNL too. Reviewed-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
