On 9/21/2017 8:43 PM, Michal Wajdeczko wrote:
On Tue, 19 Sep 2017 19:42:02 +0200, Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> wrote:From: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx> i915_slpc_info shows the contents of SLPC shared data parsed into text format. v1: Reformat slpc info (Radek) squashed query task state info in slpc info, kunmap before seq_print (Paulo) return void instead of ignored return value (Paulo) Avoid magic numbers and use local variables (Jon Bloomfield) Removed WARN_ON for checking msb of gtt address of shared gem obj. (ChrisW) Moved definition of power plan and power source to earlier patch in the series. drm/i915/slpc: Allocate/Release/Initialize SLPC shared data (Akash) v2-v3: Rebase. v4: Updated with GuC firmware v9. v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event structure. Removed unnecessary checks of vma from i915_slpc_info. Created helpers for reading the SLPC shared data and string form of SLPC state. (Sagar) Signed-off-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> ---drivers/gpu/drm/i915/i915_debugfs.c | 165 ++++++++++++++++++++++++++++++++++++1 file changed, 165 insertions(+)diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.cindex e6fd63f..7a0838f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c@@ -1023,6 +1023,170 @@ static int i915_error_state_open(struct inode *inode, struct file *file)NULL, i915_next_seqno_set, "0x%llx\n"); +static int i915_slpc_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + int i, value; + struct slpc_shared_data data; + enum slpc_global_state global_state; + enum slpc_platform_sku platform_sku; + struct slpc_task_state_data *task_data; + enum slpc_power_plan power_plan; + enum slpc_power_source power_source; + + if (!dev_priv->guc.slpc.active) + return -ENODEV; + + intel_runtime_pm_get(dev_priv); + mutex_lock(&dev_priv->pm.pcu_lock); + + intel_slpc_read_shared_data(&dev_priv->guc.slpc, &data); + + mutex_unlock(&dev_priv->pm.pcu_lock); + intel_runtime_pm_put(dev_priv); + + seq_printf(m, "shared data size: %d\n", data.shared_data_size); + + global_state = (enum slpc_global_state) data.global_state; + seq_printf(m, "global state: %d (", global_state); + seq_printf(m, "%s)\n", intel_slpc_get_state_str(global_state)); + + platform_sku = (enum slpc_platform_sku) + data.platform_info.platform_sku; + seq_printf(m, "sku: %d (", platform_sku); + switch (platform_sku) { + case SLPC_PLATFORM_SKU_UNDEFINED: + seq_puts(m, "undefined)\n"); + break; + case SLPC_PLATFORM_SKU_ULX: + seq_puts(m, "ULX)\n"); + break; + case SLPC_PLATFORM_SKU_ULT: + seq_puts(m, "ULT)\n"); + break; + case SLPC_PLATFORM_SKU_T: + seq_puts(m, "T)\n"); + break; + case SLPC_PLATFORM_SKU_MOBL: + seq_puts(m, "Mobile)\n"); + break; + case SLPC_PLATFORM_SKU_DT: + seq_puts(m, "DT)\n"); + break; + case SLPC_PLATFORM_SKU_UNKNOWN: + default: + seq_puts(m, "unknown)\n"); + break; + }Define platform_to_string() followed by single seq_puts()
Sure. Will update.
+ seq_printf(m, "slice count: %d\n", + data.platform_info.slice_count); + + seq_printf(m, "power plan/source: 0x%x\n\tplan:\t", + data.platform_info.power_plan_source); + power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN( + data.platform_info.power_plan_source); + power_source = (enum slpc_power_source) SLPC_POWER_SOURCE( + data.platform_info.power_plan_source); + switch (power_plan) { + case SLPC_POWER_PLAN_UNDEFINED: + seq_puts(m, "undefined"); + break; + case SLPC_POWER_PLAN_BATTERY_SAVER: + seq_puts(m, "battery saver"); + break; + case SLPC_POWER_PLAN_BALANCED: + seq_puts(m, "balanced"); + break; + case SLPC_POWER_PLAN_PERFORMANCE: + seq_puts(m, "performance"); + break; + case SLPC_POWER_PLAN_UNKNOWN: + default: + seq_puts(m, "unknown"); + break; + }Define power_plan_to_string() followed by single seq_puts()
Sure. Will update.
+ seq_puts(m, "\n\tsource:\t"); + switch (power_source) { + case SLPC_POWER_SOURCE_UNDEFINED: + seq_puts(m, "undefined\n"); + break; + case SLPC_POWER_SOURCE_AC: + seq_puts(m, "AC\n"); + break; + case SLPC_POWER_SOURCE_DC: + seq_puts(m, "DC\n"); + break; + case SLPC_POWER_SOURCE_UNKNOWN: + default: + seq_puts(m, "unknown\n"); + break; + } ++ seq_printf(m, "IA frequency (MHz):\n\tP0: %d\n\tP1: %d\n\tPe: %d\n\tPn: %d\n",+ data.platform_info.P0_freq * 50, + data.platform_info.P1_freq * 50, + data.platform_info.Pe_freq * 50, + data.platform_info.Pn_freq * 50); + + task_data = &data.task_state_data; + seq_printf(m, "task state data: 0x%08x 0x%08x\n", + task_data->bitfield1, task_data->bitfield2); + + seq_printf(m, "\tgtperf task active: %s\n", + yesno(task_data->gtperf_task_active)); + seq_printf(m, "\tgtperf stall possible: %s\n", + yesno(task_data->gtperf_stall_possible)); + seq_printf(m, "\tgtperf gaming mode: %s\n", + yesno(task_data->gtperf_gaming_mode)); + seq_printf(m, "\tgtperf target fps: %d\n", + task_data->gtperf_target_fps); + + seq_printf(m, "\tdcc task active: %s\n", + yesno(task_data->dcc_task_active)); + seq_printf(m, "\tin dcc: %s\n", + yesno(task_data->in_dcc)); + seq_printf(m, "\tin dct: %s\n", + yesno(task_data->in_dct)); + seq_printf(m, "\tfreq switch active: %s\n", + yesno(task_data->freq_switch_active)); + + seq_printf(m, "\tibc enabled: %s\n", + yesno(task_data->ibc_enabled)); + seq_printf(m, "\tibc active: %s\n", + yesno(task_data->ibc_active)); + seq_printf(m, "\tpg1 enabled: %s\n", + yesno(task_data->pg1_enabled)); + seq_printf(m, "\tpg1 active: %s\n", + yesno(task_data->pg1_active)); + + seq_printf(m, "\tunslice max freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->max_unslice_freq * GEN9_FREQ_SCALER)); + seq_printf(m, "\tunslice min freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->min_unslice_freq * GEN9_FREQ_SCALER)); + seq_printf(m, "\tslice max freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->max_slice_freq * GEN9_FREQ_SCALER)); + seq_printf(m, "\tslice min freq: %dMHz\n", + intel_gpu_freq(dev_priv, + task_data->min_slice_freq * GEN9_FREQ_SCALER)); + + seq_puts(m, "override parameter bitfield\n"); + for (i = 0; i < SLPC_OVERRIDE_BITFIELD_SIZE; i++) + seq_printf(m, "%d: 0x%08x\n", i, + data.override_parameters_set_bits[i]); + + seq_puts(m, "override parameters (only non-zero shown)\n"); + for (i = 0; i < SLPC_MAX_OVERRIDE_PARAMETERS; i++) { + value = data.override_parameters_values[i]; + if (value) + seq_printf(m, "%d: 0x%8x\n", i, value); + } + + return 0; +} + static int i915_frequency_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private);@@ -4899,6 +5063,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file){"i915_guc_stage_pool", i915_guc_stage_pool, 0}, {"i915_huc_load_status", i915_huc_load_status_info, 0}, {"i915_slpc_paramlist", i915_slpc_paramlist_info, 0}, + {"i915_slpc_info", i915_slpc_info, 0}, {"i915_frequency_info", i915_frequency_info, 0}, {"i915_hangcheck_info", i915_hangcheck_info, 0}, {"i915_reset_info", i915_reset_info, 0},
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