On Fri, Sep 15, 2017 at 01:03:36PM +0300, Ville Syrjälä wrote: > On Thu, Sep 14, 2017 at 09:37:37PM +0100, Chris Wilson wrote: > > Quoting Ville Syrjala (2017-09-14 16:17:31) > > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > > > i830 seems to occasionally forget the PIPESTAT enable bits when > > > we read the register. These aren't the only registers on i830 that > > > have problems with RMW, as reading the double buffered plane > > > registers returns the latched value rather than the last written > > > value. So something similar is perhaps going on with PIPESTAT. > > > > > > This corruption results on vblank interrupts occasionally turning off > > > on their own, which leads to vblank timeouts and generally a stuck > > > display subsystem. > > > > > > So let's not RMW the pipestat enable bits, and instead use the cached > > > copy we have around. > > > > > > Cc: Imre Deak <imre.deak@xxxxxxxxx> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Well it didn't make my 845g any worse. Still has > > > > [ 245.683349] [drm:pipe_config_err] *ERROR* mismatch in base.adjusted_mode.flags (2) (expected 0, found 2) > > [ 245.683382] [drm:pipe_config_err] *ERROR* mismatch in base.adjusted_mode.flags (8) (expected 0, found 8) > > [ 245.683427] pipe state doesn't match! > > > > if you are interested. > > That's a bit odd. Even if the mode originally doesn't have any > hsync/vsync flags intel_modeset_pipe_config() should give it some. > So I can't immediately see how we could manage to get there with > expected==0. Hmm. Does you 845g have DVO encoders? That could potentially explain if it ends up using intel_crtc_mode_get(). That one fails to read out the sync flags correctly, and it has other issues as well. https://patchwork.freedesktop.org/series/5183/ but not sure it applies cleanly anymore. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
