On Wed, 20 Sep 2017, Tvrtko Ursulin <tursulin@xxxxxxxxxxx> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
>
> More effort to align members on 4-byte boundary helps with
> code size a tiny bit:
>
> text data bss dec hex filename
> -1460454 60014 3656 1524124 17419c drivers/gpu/drm/i915/i915.ko
> +1460254 60014 3656 1523924 1740d4 drivers/gpu/drm/i915/i915.ko
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 20 +++++++++++++-------
> 1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0f1fe0d58a73..950aa109f8cb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -852,21 +852,27 @@ enum intel_platform {
> };
>
> struct intel_device_info {
> - u32 display_mmio_offset;
> u16 device_id;
> - u8 num_pipes;
> - u8 num_sprites[I915_MAX_PIPES];
> - u8 num_scalers[I915_MAX_PIPES];
> - u8 gen;
> u16 gen_mask;
> - enum intel_platform platform;
> +
> + u8 gen;
> u8 gt; /* GT number, 0 if undefined */
> - u8 ring_mask; /* Rings supported by the HW */
> u8 num_rings;
> + u8 ring_mask; /* Rings supported by the HW */
> +
> + enum intel_platform platform;
> +
> + u32 display_mmio_offset;
> +
> + u8 num_pipes;
> + u8 num_sprites[I915_MAX_PIPES];
> + u8 num_scalers[I915_MAX_PIPES];
> +
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
> u16 ddb_size; /* in blocks */
> +
> /* Register offsets for the various display pipes and transcoders */
> int pipe_offsets[I915_MAX_TRANSCODERS];
> int trans_offsets[I915_MAX_TRANSCODERS];
--
Jani Nikula, Intel Open Source Technology Center
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