On Mon, 2017-09-18 at 16:56 -0700, Rodrigo Vivi wrote:
> "CNL PCH chance of hang when software accesses south display
> registers after hotplug is enabled.
> Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
> south display hotplug detection."
>
> "Workaround only needs to be applied to pre-production steppings
> used in graphics capable SKUs, but it is easier to apply to
> everything, and does not hurt."
>
> v2: Moving from clock gating to right before enabling
> SHOTPLUG_CTL as it should be.
>
> Suggested-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> Cc: Ben Widawsky <ben@xxxxxxxxxxxx>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 9 ++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4d0e8f76ed1a..901832a01d52 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3218,7 +3218,14 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
>
> static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> - u32 hotplug;
> + u32 val, hotplug;
> +
> + /* Display WA #1179 WaHardHangonHotPlug: cnp */
> + if (HAS_PCH_CNP(dev_priv)) {
> + val = I915_READ(SOUTH_CHICKEN1) & ~CHASSIS_CLK_REQ_DURATION_MASK;
> + val |= CHASSIS_CLK_REQ_DURATION(0xf);
> + I915_WRITE(SOUTH_CHICKEN1, val);
> + }
>
> /* Enable digital hotplug on the PCH */
> hotplug = I915_READ(PCH_PORT_HOTPLUG);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a8cb9c17e6df..2e1cdc099f14 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7483,6 +7483,8 @@ enum {
> #define SOUTH_CHICKEN2 _MMIO(0xc2004)
> #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
> #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
> +#define CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
> +#define CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
These bit defs should be under *SOUTH_CHICKEN1*. Matches the spec
otherwise, with the definitions moved -
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> #define LPT_PWM_GRANULARITY (1<<5)
> #define DPLS_EDP_PPS_FIX_DIS (1<<0)
>
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