On Mon, Sep 18, 2017 at 07:45:14PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2017-09-18 19:25:40)
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > Pull the code to disable the port clock into a function. We already have
> > the intel_ddi_clk_select() counterpart.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 24 ++++++++++++++++--------
> > 1 file changed, 16 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 93cbbcbbc193..2b4de7d03ff0 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2131,6 +2131,21 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> > }
> > }
> >
> > +static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + enum port port = encoder->port;
>
> port was previously intel_ddi_get_encoder_port(encoder).
encoder->port is fine in this case. The main two reasons for
the existence of intel_ddi_get_encoder_port() were FDI and MST.
The FDI problem disappeared as soon as we got encoder->port.
Previously we only had dig_port->port, and FDI doesn't have a
dig_port. In fact we should try to eliminate dig_port->port since
it's redundant now.
Hmm. And we even populate encoder->port for the fake MST encoders
so even that shouldn't pose a problem anymore. But in this case
we actually get passed the "real" DP encoder (ie. mst->primary)
so even if encoder->port wasn't populated for the fake MST encoders
this would still work.
I have another patch in the series to convert a lot more
intel_ddi_get_encoder_port()s into encoder->port. But that patch
is near the end, and apparently I already converted some of them
along the way.
I guess I should at leaast add some notes to the commit messages
whenever I'm doing this.
>
> > +
> > + if (IS_CANNONLAKE(dev_priv))
> > + I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> > + DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> > + else if (IS_GEN9_BC(dev_priv))
> > + I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
> > + DPLL_CTRL2_DDI_CLK_OFF(port));
> > + else if (INTEL_GEN(dev_priv) < 9)
> > + I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
> > +}
--
Ville Syrjälä
Intel OTC
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