On Thu, Sep 14, 2017 at 06:31:39PM +0000, Manasi Navare wrote:
> No functional changes. Only change the macro from
> "DPLL_CFGCR0_DC0_FRAC_SHIFT to DPLL_CFGCR0_DCO_FRACTION_SHIFT
> to be consistent with DPLL_CFGCR0_DCO_FRACTION_MASK
> and DPLL_CFGCR0_DCO_FRACTION
>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0befefe..94b40a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8599,7 +8599,7 @@ enum skl_power_gate {
> #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
> #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
> #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
> -#define DPLL_CFGCR0_DCO_FRAC_SHIFT (10)
> +#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
> #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
> #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
> #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 1da3bb2..31d1458 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1212,7 +1212,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
>
> dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> - DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;
> + DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
>
> return dco_freq / (p0 * p1 * p2 * 5);
> }
> --
> 2.1.4
>
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