Thanks for that. :) Have a nice day. :) -----Original Message----- From: Joonas Lahtinen [mailto:joonas.lahtinen@xxxxxxxxxxxxxxx] Sent: Thursday, September 14, 2017 4:48 PM To: Wang, Zhi A <zhi.a.wang@xxxxxxxxx>; intel-gfx@xxxxxxxxxxxxxxxxxxxxx; intel-gvt-dev@xxxxxxxxxxxxxxxxxxxxx Cc: chris@xxxxxxxxxxxxxxxxxx; zhenyuw@xxxxxxxxxxxxxxx; Widawsky, Benjamin <benjamin.widawsky@xxxxxxxxx>; Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx> Subject: Re: [PATCH v17 1/4] drm/i915: Introduce private PAT management On Thu, 2017-09-14 at 20:39 +0800, Zhi Wang wrote: > The private PAT management is to support PPAT entry manipulation. Two > APIs are introduced for dynamically managing PPAT entries: > intel_ppat_get and intel_ppat_put. > > intel_ppat_get will search for an existing PPAT entry which perfectly > matches the required PPAT value. If not, it will try to allocate a new > entry if there is any available PPAT indexs, or return a partially > matched PPAT entry if there is no available PPAT indexes. > > intel_ppat_put will put back the PPAT entry which comes from > intel_ppat_get. If it's dynamically allocated, the reference count > will be decreased. If the reference count turns into zero, the PPAT > index is freed again. > > Besides, another two callbacks are introduced to support the private > PAT management framework. One is ppat->update_hw(), which writes the > PPAT configurations in ppat->entries into HW. Another one is > ppat->match, which will return a score to show how two PPAT values match with each other. > I manually fixed the enum to use BIT() and merged the first two patches of the series. The third should go in with the kselftests. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
