Quoting Ville Syrjala (2017-09-13 15:08:55) > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Use the passed in crtc state rather than crtc->config when configuring > the DPLL on VLV/CHV. > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index ef836fe3eacd..23fead59b825 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5831,11 +5831,11 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, > intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); Missed intel_crtc_has_dp_encoder(intel_crtc->config) ? > > if (IS_CHERRYVIEW(dev_priv)) { > - chv_prepare_pll(intel_crtc, intel_crtc->config); > - chv_enable_pll(intel_crtc, intel_crtc->config); > + chv_prepare_pll(intel_crtc, pipe_config); > + chv_enable_pll(intel_crtc, pipe_config); > } else { > - vlv_prepare_pll(intel_crtc, intel_crtc->config); > - vlv_enable_pll(intel_crtc, intel_crtc->config); > + vlv_prepare_pll(intel_crtc, pipe_config); > + vlv_enable_pll(intel_crtc, pipe_config); > } > > intel_encoders_pre_enable(crtc, pipe_config, old_state); > @@ -6735,8 +6735,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, > > /* Set HBR and RBR LPF coefficients */ > if (pipe_config->port_clock == 162000 || > - intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || > - intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) > + intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) || > + intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) > vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), > 0x009f0003); > else > @@ -6763,7 +6763,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, > > coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); > coreclk = (coreclk & 0x0000ff00) | 0x01c00000; > - if (intel_crtc_has_dp_encoder(crtc->config)) > + if (intel_crtc_has_dp_encoder(pipe_config)) > coreclk |= 0x01000000; > vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx