Re: [PATCH 2/3] drm/i915: Unify skylake plane update

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On Tue, Sep 12, 2017 at 12:19:39PM +0300, Juha-Pekka Heikkila wrote:
> Don't handle skylake primary plane separately as it is similar
> plane as the others.
> 
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@xxxxxxxxx>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  8 ++++
>  drivers/gpu/drm/i915/intel_display.c | 85 +-----------------------------------
>  drivers/gpu/drm/i915/intel_drv.h     |  9 ++--
>  drivers/gpu/drm/i915/intel_fbc.c     | 11 +++--
>  drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
>  5 files changed, 22 insertions(+), 93 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d07d110..24d52d70 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1096,6 +1096,14 @@ struct intel_fbc {
>  			int src_w;
>  			int src_h;
>  			bool visible;
> +			/*
> +			 * Display surface base address adjustement for
> +			 * pageflips. Note that on gen4+ this only adjusts up
> +			 * to a tile, offsets within a tile are handled in
> +			 * the hw itself (with the TILEOFF register).
> +			 */
> +			int adjusted_x;
> +			int adjusted_y;

Please split this into two patches. First one should nuke the
adjusted_x/y from the crtc, the second should do the skl function
unification.

>  		} plane;
>  
>  		struct {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0dd0e2a..739003d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3298,7 +3298,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  				      const struct intel_plane_state *plane_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	const struct drm_framebuffer *fb = plane_state->base.fb;
>  	enum plane plane = primary->plane;
>  	u32 linear_offset;
> @@ -3316,9 +3315,6 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
>  	else
>  		dspaddr_offset = linear_offset;
>  
> -	crtc->adjusted_x = x;
> -	crtc->adjusted_y = y;
> -
>  	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>  
>  	if (INTEL_GEN(dev_priv) < 4) {
> @@ -3554,83 +3550,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  	return plane_ctl;
>  }
>  
> -static void skylake_update_primary_plane(struct intel_plane *plane,
> -					 const struct intel_crtc_state *crtc_state,
> -					 const struct intel_plane_state *plane_state)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	const struct drm_framebuffer *fb = plane_state->base.fb;
> -	enum plane_id plane_id = plane->id;
> -	enum pipe pipe = plane->pipe;
> -	u32 plane_ctl = plane_state->ctl;
> -	unsigned int rotation = plane_state->base.rotation;
> -	u32 stride = skl_plane_stride(fb, 0, rotation);
> -	u32 aux_stride = skl_plane_stride(fb, 1, rotation);
> -	u32 surf_addr = plane_state->main.offset;
> -	int scaler_id = plane_state->scaler_id;
> -	int src_x = plane_state->main.x;
> -	int src_y = plane_state->main.y;
> -	int src_w = drm_rect_width(&plane_state->base.src) >> 16;
> -	int src_h = drm_rect_height(&plane_state->base.src) >> 16;
> -	int dst_x = plane_state->base.dst.x1;
> -	int dst_y = plane_state->base.dst.y1;
> -	int dst_w = drm_rect_width(&plane_state->base.dst);
> -	int dst_h = drm_rect_height(&plane_state->base.dst);
> -	unsigned long irqflags;
> -
> -	/* Sizes are 0 based */
> -	src_w--;
> -	src_h--;
> -	dst_w--;
> -	dst_h--;
> -
> -	crtc->dspaddr_offset = surf_addr;
> -
> -	crtc->adjusted_x = src_x;
> -	crtc->adjusted_y = src_y;
> -
> -	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> -
> -	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> -		I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
> -			      PLANE_COLOR_PIPE_GAMMA_ENABLE |
> -			      PLANE_COLOR_PIPE_CSC_ENABLE |
> -			      PLANE_COLOR_PLANE_GAMMA_DISABLE);
> -	}
> -
> -	I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
> -	I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
> -	I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
> -	I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
> -	I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
> -		      (plane_state->aux.offset - surf_addr) | aux_stride);
> -	I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
> -		      (plane_state->aux.y << 16) | plane_state->aux.x);
> -
> -	if (scaler_id >= 0) {
> -		uint32_t ps_ctrl = 0;
> -
> -		WARN_ON(!dst_w || !dst_h);
> -		ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
> -			crtc_state->scaler_state.scalers[scaler_id].mode;
> -		I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
> -		I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
> -		I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
> -		I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
> -		I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
> -	} else {
> -		I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
> -	}
> -
> -	I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
> -		      intel_plane_ggtt_offset(plane_state) + surf_addr);
> -
> -	POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
> -
> -	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> -}
> -
>  static void skylake_disable_primary_plane(struct intel_plane *primary,
>  					  struct intel_crtc *crtc)
>  {
> @@ -13230,7 +13149,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		num_formats = ARRAY_SIZE(skl_primary_formats);
>  		modifiers = skl_format_modifiers_ccs;
>  
> -		primary->update_plane = skylake_update_primary_plane;
> +		primary->update_plane = skl_update_plane;
>  		primary->disable_plane = skylake_disable_primary_plane;
>  	} else if (INTEL_GEN(dev_priv) >= 9) {
>  		intel_primary_formats = skl_primary_formats;
> @@ -13240,7 +13159,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		else
>  			modifiers = skl_format_modifiers_noccs;
>  
> -		primary->update_plane = skylake_update_primary_plane;
> +		primary->update_plane = skl_update_plane;
>  		primary->disable_plane = skylake_disable_primary_plane;
>  	} else if (INTEL_GEN(dev_priv) >= 4) {
>  		intel_primary_formats = i965_primary_formats;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d58cd10..a690cc5 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -803,12 +803,6 @@ struct intel_crtc {
>  	unsigned long long enabled_power_domains;
>  	struct intel_overlay *overlay;
>  
> -	/* Display surface base address adjustement for pageflips. Note that on
> -	 * gen4+ this only adjusts up to a tile, offsets within a tile are
> -	 * handled in the hw itself (with the TILEOFF register). */
> -	int adjusted_x;
> -	int adjusted_y;
> -
>  	struct intel_crtc_state *config;
>  
>  	/* global reset count when the last flip was submitted */
> @@ -1918,6 +1912,9 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
>  			      struct drm_file *file_priv);
>  void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
>  void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
> +void skl_update_plane(struct intel_plane *plane,
> +		      const struct intel_crtc_state *crtc_state,
> +		      const struct intel_plane_state *plane_state);
>  
>  /* intel_tv.c */
>  void intel_tv_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 58a772d..dc059808 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
>   */
>  static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
>  {
> -	return crtc->base.y - crtc->adjusted_y;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	struct intel_fbc *fbc = &dev_priv->fbc;
> +
> +	return crtc->base.y - fbc->state_cache.plane.adjusted_y;

As I said earlier, we'll want to get rid if this crtc->base.y thing as
well. I think it's actually semi broken at the moment since we seem to
be stuffing the unclipped coordinate in there. It should really be
the clipped one (ie. plane_state->src.y1 >> 16). So we'll want to put
that (or potentially the whole fence_offset) into the fbc cache as well.
I guess we could do that part as a separate patch though.

While I was looking at the fbc code it occurred to me that it's doing
way too much checking in the can_activate() function. Most of the checks
it's doing there we could have done already when we had the plane/crtc
states around. So I think we should pre-compute more of the answer to the 
"can this plane/crtc do fbc?" question. It might allow us to nuke some
stuff from the fbc state cache as well.

>  }
>  
>  /*
> @@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
>  
>  	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
>  					&effective_h);
> -	effective_w += crtc->adjusted_x;
> -	effective_h += crtc->adjusted_y;
> +	effective_w += fbc->state_cache.plane.adjusted_x;
> +	effective_h += fbc->state_cache.plane.adjusted_y;
>  
>  	return effective_w <= max_w && effective_h <= max_h;
>  }
> @@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
>  	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
>  	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
>  	cache->plane.visible = plane_state->base.visible;
> +	cache->plane.adjusted_x = plane_state->main.x;
> +	cache->plane.adjusted_y = plane_state->main.y;
>  
>  	if (!cache->plane.visible)
>  		return;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index b0d6e3e..2ec4108 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -224,7 +224,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>  #endif
>  }
>  
> -static void
> +void
>  skl_update_plane(struct intel_plane *plane,
>  		 const struct intel_crtc_state *crtc_state,
>  		 const struct intel_plane_state *plane_state)
> -- 
> 2.7.4
> 
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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