Only PPAT entries 0/2/3/4 are using. Remove extra PPAT entry allocation
during initialization.
v8:
- Move ppat_index() into i915_gem_gtt.c. (Chris)
- Change the name of ppat_bits_to_index to ppat_index.
Cc: Ben Widawsky <benjamin.widawsky@xxxxxxxxx>
Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Suggested-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Signed-off-by: Zhi Wang <zhi.a.wang@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 53 +++++++++++++++++++------------------
1 file changed, 27 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7948119..9cf60e5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2979,6 +2979,13 @@ static unsigned int chv_private_pat_match(u8 src, u8 dst)
INTEL_PPAT_PERFECT_MATCH : 0;
}
+/* PPAT index = 4 * PAT + 2 * PCD + PWT */
+static inline unsigned int ppat_index(unsigned int bits)
+{
+ return (4 * !!(bits & _PAGE_PAT) + 2 * !!(bits & _PAGE_PCD)
+ + !!(bits & _PAGE_PWT));
+}
+
static void cnl_setup_private_ppat(struct intel_ppat *ppat)
{
ppat->max_entries = 8;
@@ -2988,18 +2995,15 @@ static void cnl_setup_private_ppat(struct intel_ppat *ppat)
/* XXX: spec is unclear if this is still needed for CNL+ */
if (!USES_PPGTT(ppat->i915)) {
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_UC);
return;
}
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
- __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
- __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
- __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
- __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
- __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
- __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
- __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+ /* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_WB | GEN8_PPAT_LLC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), GEN8_PPAT_UC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
}
/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
@@ -3026,18 +3030,18 @@ static void bdw_setup_private_ppat(struct intel_ppat *ppat)
* So we can still hold onto all our assumptions wrt cpu
* clflushing on LLC machines.
*/
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_UC);
return;
}
- __alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC); /* for normal objects, no eLLC */
- __alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); /* for something pointing to ptes? */
- __alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); /* for scanout with eLLC */
- __alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC); /* Uncached objects, mostly for scanout */
- __alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
- __alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
- __alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
- __alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
+ /* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+ /* for normal objects, no eLLC */
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), GEN8_PPAT_WB | GEN8_PPAT_LLC);
+ /* for scanout with eLLC */
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
+ /* Uncached objects, mostly for scanout */
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), GEN8_PPAT_UC);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
}
static void chv_setup_private_ppat(struct intel_ppat *ppat)
@@ -3066,14 +3070,11 @@ static void chv_setup_private_ppat(struct intel_ppat *ppat)
* in order to keep the global status page working.
*/
- __alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
- __alloc_ppat_entry(ppat, 1, 0);
- __alloc_ppat_entry(ppat, 2, 0);
- __alloc_ppat_entry(ppat, 3, 0);
- __alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
- __alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
- __alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
- __alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
+ /* See gen8_pte_encode() for the mapping from cache-level to PPAT */
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED_PDE), CHV_PPAT_SNOOP);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_DISPLAY_ELLC), 0);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_UNCACHED), 0);
+ __alloc_ppat_entry(ppat, ppat_index(PPAT_CACHED), CHV_PPAT_SNOOP);
}
static void gen6_gmch_remove(struct i915_address_space *vm)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
