Quoting Sagar Arun Kamble (2017-09-01 08:25:05)
> +/*
> + * This function enables RPS and RC6 for platforms prior to GEN9 and
> + * enables only RPS for GEN9+.
> + */
> +void __intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> {
> /* We shouldn't be disabling as we submit, so this should be less
> * racy than it appears!
> */
> - if (READ_ONCE(dev_priv->rps.enabled))
> + if (READ_ONCE(dev_priv->rps.rps_enabled))
> return;
>
> - /* Powersaving is controlled by the host when inside a VM */
> - if (intel_vgpu_active(dev_priv))
> - return;
> -
> - mutex_lock(&dev_priv->rps.hw_lock);
> -
> if (IS_CHERRYVIEW(dev_priv)) {
> cherryview_enable_rps(dev_priv);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> valleyview_enable_rps(dev_priv);
> } else if (INTEL_GEN(dev_priv) >= 9) {
> - gen9_enable_rc6(dev_priv);
> gen9_enable_rps(dev_priv);
> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> - gen6_update_ring_freq(dev_priv);
> } else if (IS_BROADWELL(dev_priv)) {
> gen8_enable_rps(dev_priv);
> gen6_update_ring_freq(dev_priv);
> @@ -7878,10 +7891,35 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
> WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
>
> - dev_priv->rps.enabled = true;
> + dev_priv->rps.rps_enabled = true;
> +}
> +
> +void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> +{
> + /* Powersaving is controlled by the host when inside a VM */
> + if (intel_vgpu_active(dev_priv))
> + return;
> +
> + mutex_lock(&dev_priv->rps.hw_lock);
> +
> + if (INTEL_GEN(dev_priv) >= 9) {
> + if (!READ_ONCE(dev_priv->rps.rc6_enabled))
> + gen9_enable_rc6(dev_priv);
> + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> + gen6_update_ring_freq(dev_priv);
> + }
> + __intel_enable_gt_powersave(dev_priv);
> +
> mutex_unlock(&dev_priv->rps.hw_lock);
> }
Ok, still nowhere close to being separate. Let's see if I can find the
patches I had to start making rc6 separate from rps.
-Chris
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