On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote: > We also see the delayed GTT write issue on i915g/i915gm, so let's > presume that it is a universal problem for all llc machines, and that we > just haven't yet noticed on g33, gen4 and gen5 machines. > > Testcase: igt/gem_mmap_gtt/coherency # i915gm That fails on my i945gm as well. mmio read before the clfush does seem to cure it. Doing the mmio after the clflush still fails. I wonder if there's some prefetching going on or why exactly it behaves that way... > References: https://bugs.freedesktop.org/show_bug.cgi?id=102577 > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 4dffebae5601..350b761b9e91 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -694,7 +694,7 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) > > switch (obj->base.write_domain) { > case I915_GEM_DOMAIN_GTT: > - if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) { > + if (!HAS_LLC(dev_priv)) { > intel_runtime_pm_get(dev_priv); > spin_lock_irq(&dev_priv->uncore.lock); > POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); There's no documented register at that offset on gen2/3. Might be less risky to read something we know to actually exist. > -- > 2.14.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
