On Wed, Aug 30, 2017 at 06:14:03PM +0000, Pandiyan, Dhinakaran wrote:
>
> On Wed, 2017-08-16 at 17:54 -0700, Rodrigo Vivi wrote:
> > This is heavily based on a initial patch provided by Ville
> > plus all changes provided later by Ander.
> >
>
> Ville abandoned this change last time stating - "Assume 1 pixel per
> clock for the purposes of max pixel rate calculation until DDI clock
> voltage scaling is handled"
>
> If you can confirm that change was implemented, this patch is
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
>
>
> Also, I see that Ville's patch to change the pixel rate checks to use
> cdclk has not been merged
I totally forgot about that one TBH. I've just reposted first patch to
get a fresh CI run for it.
I think this CNL thing might look cleaner if redone on top of my stuff,
but if people want this in ASAP I can rebase my stuff as well.
>
>
>
> > As Geminilake, Cannonlake also supports 2 pixels per clock.
> >
> > Different from Geminilake we are not implementing the 99% Wa.
> > But we can revisit that decision later if we find out
> > any limitation on later CNL SKUs.
> >
> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> > Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++------
> > drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> > 2 files changed, 8 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 1241e5891b29..6b1d805fb755 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1422,9 +1422,9 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> >
> > static int cnl_calc_cdclk(int max_pixclk)
> > {
> > - if (max_pixclk > 336000)
> > + if (max_pixclk > 2 * 336000)
> > return 528000;
> > - else if (max_pixclk > 168000)
> > + else if (max_pixclk > 2 * 168000)
> > return 336000;
> > else
> > return 168000;
> > @@ -1752,9 +1752,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > crtc_state->has_audio &&
> > crtc_state->port_clock >= 540000 &&
> > crtc_state->lane_count == 4) {
> > - if (IS_CANNONLAKE(dev_priv))
> > - pixel_rate = max(316800, pixel_rate);
> > - else if (IS_GEMINILAKE(dev_priv))
> > + if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> > pixel_rate = max(2 * 316800, pixel_rate);
> > else
> > pixel_rate = max(432000, pixel_rate);
> > @@ -1766,7 +1764,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > * two pixels per clock.
> > */
> > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
> > - if (IS_GEMINILAKE(dev_priv))
> > + if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> > pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > else
> > pixel_rate = max(2 * 96000, pixel_rate);
> > @@ -1999,6 +1997,8 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > {
> > int max_cdclk_freq = dev_priv->max_cdclk_freq;
> >
> > + if (IS_CANNONLAKE(dev_priv))
> > + return 2 * max_cdclk_freq;
> > if (IS_GEMINILAKE(dev_priv))
> > /*
> > * FIXME: Limiting to 99% as a temporary workaround. See
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ed662937ec3c..42f753df30cb 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3969,7 +3969,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> > crtc_clock = crtc_state->adjusted_mode.crtc_clock;
> > dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
> >
> > - if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> > + if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)) ||
> > + IS_CANNONLAKE(to_i915(intel_crtc->base.dev)))
> > dotclk *= 2;
> >
> > pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
--
Ville Syrjälä
Intel OTC
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