On Tue, 2017-08-29 at 16:09 -0700, Rodrigo Vivi wrote: > Driver’s CPU access to GTT is via the GTTMMADR BAR. > > The current HW implementation of that BAR is to only > support <= DW (and maybe QW) writes—not 16/32/64B writes > that could occur with WC and/or SSE/AVX moves. > > GTTMMADR must be marked uncacheable (UC). > Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry). > > v2: Get clarification on the reasons and spec is getting > updated to reflect it now. > > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > Suggested-by: Ben Widawsky <benjamin.widawsky@xxxxxxxxx> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> Rodrigo, can you double-check how this interacts with the patch from Zhi that adds the WB flag to PPAT_CACHE_INDEX on CNL. If that doesn't help with the problem, this is; Reviewed-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
