Since this on has no functional change and passed ci and is rv-b I
merged patch 1 to dinq already
Thanks for patch and review.
For next time it would be good to send separated patches since patches
1 and 2 have no directly relation...
So CI test them individually.
On Thu, Aug 24, 2017 at 3:28 AM, Kamble, Sagar A
<sagar.a.kamble@xxxxxxxxx> wrote:
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
>
> -----Original Message-----
> From: Mateo Lozano, Oscar
> Sent: Thursday, August 24, 2017 5:28 AM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Mateo Lozano, Oscar <oscar.mateo@xxxxxxxxx>; Kamble, Sagar A <sagar.a.kamble@xxxxxxxxx>; Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx>
> Subject: [PATCH 1/2] drm/i915: Make some RPS functions static
>
> They are not used anywhere else. Also, fix a small typo in a comment.
>
> No functional changes.
>
> Cc: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: Oscar Mateo <oscar.mateo@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 8 ++++----
> drivers/gpu/drm/i915/intel_drv.h | 3 ---
> 2 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e21ce9c..5d391e6 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -336,7 +336,7 @@ void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
> __gen6_mask_pm_irq(dev_priv, mask);
> }
>
> -void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
> +static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
> {
> i915_reg_t reg = gen6_pm_iir(dev_priv);
>
> @@ -347,7 +347,7 @@ void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
> POSTING_READ(reg);
> }
>
> -void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
> +static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
> {
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -357,7 +357,7 @@ void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
> /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
> }
>
> -void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
> +static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
> {
> lockdep_assert_held(&dev_priv->irq_lock);
>
> @@ -405,7 +405,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
> synchronize_irq(dev_priv->drm.irq);
>
> /* Now that we will not be generating any more work, flush any
> - * outsanding tasks. As we are called on the RPS idle path,
> + * outstanding tasks. As we are called on the RPS idle path,
> * we will reset the GPU to minimum frequencies, so the current
> * state of the worker can be discarded.
> */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f60995f..74c1860 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1206,11 +1206,8 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
> /* i915_irq.c */
> void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
> void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
> -void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
> void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
> void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
> -void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
> -void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
> void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
> void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
> void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
> --
> 1.9.1
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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