Quoting Mika Kuoppala (2017-08-08 14:36:39) > Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > > As we may have just bound the renderstate into the GGTT for execution, we > > need to ensure that the GTT TLB are also flushed. > > > > On snb-gt2, this would cause a random GPU hang at the start of a new > > context (e.g. boot) and on snb-gt1, it was causing the renderstate batch > > to take ~10s. It was the GPU hang that revealed the truth, as the CS > > gleefully executed beyond the end of the golden renderstate batch, a good > > indicator for a GTT TLB miss. > > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > > Cc: stable@xxxxxxxxxxxxxxx > > The flush has been there but got stomped by: > > Fixes: dc4be6071a24 ("drm/i915: Add explicit request management to i915_gem_init_hw()") Hmm, I think it is actually 20fe17aa52dc ("drm/i915: Remove redundant TLB invalidate on switching contexts"). The importance is in having the invalidate after the GTT bind and before the MI_BB_START. Which just happens to be implied by the ordering of the context switch emission, but given the indirect link, not guaranteed. Commit dc4be6071a24 only modifies the sequence after the MI_BB_START, so doesn't look like the culprit. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx