On Thu, Aug 03, 2017 at 03:51:37PM -0700, Rodrigo Vivi wrote:
> DDI_E is not supported on CNL-U and CNL-Y
>
> When adding the inital support we noticed DDI_E wasn't supported
> and removed it on v4 and v5 of that patch.
> However for some reason I missed or put back these 2 chunks.
>
> Time to clean it up to avoid later confusion.
>
> Fixes: 8bcd3dd41766 ("drm/i915/cnl: Add power wells for CNL")
> Cc: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Looks ok and also the correct thing for CNL_H/S, where the port E DDI
power well is separate from port A and not dependent on power well #2
(unlike SKL):
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 347484ed6d2c..e77e84a6fd2f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1796,7 +1796,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> BIT_ULL(POWER_DOMAIN_AUX_D) | \
> @@ -1805,7 +1804,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_INIT))
> #define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
> --
> 2.13.2
>
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