Hello, Found there might be a corner case for intel_lrc_irq_handler() in a dead loop, want to understand if this can be real or not. The scenario is like: 1. Write wedged to trigger a GPU reset; 2. meanwhile, there is one ongoing request in port[0], and its context switch interrupt is generated from HW; 3. as interrupt line is disabled during GPU reset, it is possible that this interrupt is not handled by intel_lrc_irq_handler(); 4. during GPU reset, the CSB tail is reset to 0x7 which is a default value; 5. i915 try to replay this request during GPU reset; 6. GPU reset completed; 7. handling the pending interrupt of the step#2. Normally as in step#5 driver wrote the ELSP and replayed a request so the CSB tail should be updated to 0 in step#7. But if the CSB tail updating is not that quick, in step#7 when handling the last pending interrupt the CSB tail is still 0x7, the intel_lrc_irq_handler() will be in a dead loop then. If the CSB tail updating is not synchronized with the ELSP writing then my understanding is that it is possible to encounter this corner case. If so, shall we clear the pending interrupts in IIR during i915_reset? Please correct me if anything wrong. Thanks Chuanxiao _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
