> -----Original Message-----
> From: Paauwe, Bob J
> Sent: Saturday, July 29, 2017 1:55 AM
> To: Srinivas, Vidya <vidya.srinivas@xxxxxxxxx>
> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH 5/8] drm/i915: Upscale scaler max scale for
> NV12
>
> On Mon, 24 Jul 2017 09:57:46 +0530
> Vidya Srinivas <vidya.srinivas@xxxxxxxxx> wrote:
>
> > From: Chandra Konduru <chandra.konduru@xxxxxxxxx>
> >
> > This patch updates scaler max limit support for NV12
> >
> > v2: Rebased (me)
> >
> > v3: Rebased (me)
> >
> > v4: Missed the Tested-by/Reviewed-by in the previous series
> > Adding the same to commit message in this version.
> >
> > v5: Addressed review comments from Ville and rebased
> > - calculation of max_scale to be made
> > less convoluted by splitting it up a bit
>
> I think the splitting up of the function isn't correct, see below.
>
> > - Indentation errors to be fixed in the series
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@xxxxxxxxx>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@xxxxxxxxx>
> > Signed-off-by: Chandra Konduru <chandra.konduru@xxxxxxxxx>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@xxxxxxxxx>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++----
> ------
> > drivers/gpu/drm/i915/intel_drv.h | 3 ++-
> > drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
> > 3 files changed, 27 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 2d3069c..390ef5c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3426,6 +3426,8 @@ static u32 skl_plane_ctl_format(uint32_t
> pixel_format)
> > return PLANE_CTL_FORMAT_YUV422 |
> PLANE_CTL_YUV422_UYVY;
> > case DRM_FORMAT_VYUY:
> > return PLANE_CTL_FORMAT_YUV422 |
> PLANE_CTL_YUV422_VYUY;
> > + case DRM_FORMAT_NV12:
> > + return PLANE_CTL_FORMAT_NV12;
> > default:
> > MISSING_CASE(pixel_format);
> > }
> > @@ -4671,7 +4673,8 @@ static void cpt_verify_modeset(struct
> drm_device
> > *dev, int pipe) static int skl_update_scaler(struct intel_crtc_state
> > *crtc_state, bool force_detach,
> > unsigned int scaler_user, int *scaler_id,
> > - int src_w, int src_h, int dst_w, int dst_h)
> > + int src_w, int src_h, int dst_w, int dst_h,
> > + uint32_t pixel_format)
> > {
> > struct intel_crtc_scaler_state *scaler_state =
> > &crtc_state->scaler_state;
> > @@ -4687,7 +4690,8 @@ static void cpt_verify_modeset(struct
> drm_device *dev, int pipe)
> > * the 90/270 degree plane rotation cases (to match the
> > * GTT mapping), hence no need to account for rotation here.
> > */
> > - need_scaling = src_w != dst_w || src_h != dst_h;
> > + need_scaling = src_w != dst_w || src_h != dst_h ||
> > + (pixel_format == DRM_FORMAT_NV12);
> >
> > /*
> > * Scaling/fitting not supported in IF-ID mode in GEN9+ @@ -4763,7
> > +4767,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
> > return skl_update_scaler(state, !state->base.active,
> SKL_CRTC_INDEX,
> > &state->scaler_state.scaler_id,
> > state->pipe_src_w, state->pipe_src_h,
> > - adjusted_mode->crtc_hdisplay, adjusted_mode-
> >crtc_vdisplay);
> > + adjusted_mode->crtc_hdisplay, adjusted_mode-
> >crtc_vdisplay, 0);
> > }
> >
> > /**
> > @@ -4793,7 +4797,8 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> > drm_rect_width(&plane_state->base.src) >>
> 16,
> > drm_rect_height(&plane_state->base.src) >>
> 16,
> > drm_rect_width(&plane_state->base.dst),
> > - drm_rect_height(&plane_state->base.dst));
> > + drm_rect_height(&plane_state->base.dst),
> > + fb ? fb->format->format : 0);
> >
> > if (ret || plane_state->scaler_id < 0)
> > return ret;
> > @@ -4819,6 +4824,7 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> > case DRM_FORMAT_YVYU:
> > case DRM_FORMAT_UYVY:
> > case DRM_FORMAT_VYUY:
> > + case DRM_FORMAT_NV12:
> > break;
> > default:
> > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported
> scaling format
> > 0x%x\n", @@ -12674,11 +12680,12 @@ static int
> > intel_atomic_commit(struct drm_device *dev, }
> >
> > int
> > -skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
> > *crtc_state)
> > +skl_max_scale(struct intel_crtc *intel_crtc,
> > + struct intel_crtc_state *crtc_state, uint32_t pixel_format)
> > {
> > struct drm_i915_private *dev_priv;
> > - int max_scale;
> > - int crtc_clock, max_dotclk;
> > + int max_scale, mult;
> > + int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
> >
> > if (!intel_crtc || !crtc_state->base.enable)
> > return DRM_PLANE_HELPER_NO_SCALING; @@ -12700,8
> +12707,10 @@ static
> > int intel_atomic_commit(struct drm_device *dev,
> > * or
> > * cdclk/crtc_clock
> > */
> > - max_scale = min((1 << 16) * 3 - 1,
> > - (1 << 8) * ((max_dotclk << 8) / crtc_clock));
> > + mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
> > + tmpclk1 = (1 << 16) * (mult - 1);
>
> I don't think the above calculation is right, at least it's not matching what
> was being done previously.
>
> Originally it did ((1 << 16) * 3) - 1 which is 0x2ffff
>
> Now it does (1 << 16) * (3 - 1) which is 0x20000
>
Thank you so much.
I will fix the error and resubmit the patch.
Regards
Vidya
>
> > + tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> > + max_scale = min(tmpclk1, tmpclk2);
> >
> > return max_scale;
> > }
> > @@ -12722,7 +12731,11 @@ static int intel_atomic_commit(struct
> drm_device *dev,
> > /* use scaler when colorkey is not required */
> > if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
> > min_scale = 1;
> > - max_scale = skl_max_scale(to_intel_crtc(crtc),
> crtc_state);
> > + max_scale = skl_max_scale(to_intel_crtc(crtc),
> > + crtc_state,
> > + state->base.fb ?
> > + state->base.fb->format-
> >format :
> > + 0);
> > }
> > can_position = true;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 021cc54..6f9c631 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1456,7 +1456,8 @@ void intel_mode_from_pipe_config(struct
> drm_display_mode *mode,
> > struct intel_crtc_state *pipe_config);
> >
> > int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); -int
> > skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
> > *crtc_state);
> > +int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
> *crtc_state,
> > + uint32_t pixel_format);
> >
> > static inline u32 intel_plane_ggtt_offset(const struct
> > intel_plane_state *state) { diff --git
> > a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index a38b4f3..24f769a 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -817,7 +817,8 @@ static u32 g4x_sprite_ctl(const struct
> intel_crtc_state *crtc_state,
> > if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
> > can_scale = 1;
> > min_scale = 1;
> > - max_scale = skl_max_scale(crtc, crtc_state);
> > + max_scale = skl_max_scale(crtc, crtc_state,
> > + fb->format->format);
> > } else {
> > can_scale = 0;
> > min_scale = DRM_PLANE_HELPER_NO_SCALING;
>
>
>
> --
> --
> Bob Paauwe
> Bob.J.Paauwe@xxxxxxxxx
> IOTG / PED Software Organization
> Intel Corp. Folsom, CA
> (916) 356-6193
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